Automatic white adjusting circuit for a television camera

• US 4,486,771 A
• Filed: 03/14/1983
• Issued: 12/04/1984
• Est. Priority Date: 06/02/1980
• Status: Expired due to Fees

• Current Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Original Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Inventors: Machida, Toyotaka, Ikemura, Yuichi, Noda, Teruaki
• Primary Examiner(s): Chin, Tommy P.
• Application Number:
  US06/475,216
• Time in Patent Office: 631 Days
• Field of Search: 358/29, 358/10, 358/139, 358/168, 358/169, 358/209
• US Class Current: 348/228.1
• CPC Class Codes: H04N 23/88 for colour balance, e.g. white-balance circuits or colour temperature control

Abstract

An automatic white adjusting circuit for a television camera in which a rough adjustment is first performed with an adjustment quantity of large steps, and fine adjustment is secondly performed with an adjustment quantity of small steps, upon automatic adjustment of the white by performing such operations as directing the television camera towards a white surface. According to the automatic white adjusting circuit of the present invention, the adjusting accuracy of the white balance can be improved, and the white adjustment can be performed automatically within a short period of time.

Claims

1. An automatic white adjusting circuit for a television camera having a color image pick-up device, said automatic white adjusting circuit comprising:

first variable gain amplifying means applied with a first primary color signal;

second variable gain amplifying means applied with a second primary color signal,

matrixing means applied with a third primary color signal and outputs of said first and second variable gain amplifying means;

first, second, and third low-pass filters respectively applied with the outputs of said first and second variable gain amplifying means and said third primary color signal;

first and second comparing means respectivey supplied with an output of said third low-pass filter to a single input terminal, and supplied with respective outputs of said first and second low-pass filters to their respective other input terminal;

first and third reversible counter means respectivel supplied with an output of said first comparing means to their respective up/down input terminals;

second and fourth reversible counter means respectively supplied with an output of said second comparing means to their respective up/down input terminals;

first, second, third and fourth digital-to-analog converters respectively supplied with parallel outputs of said first, second, third, and fourth reversible counter means;

first reference gain establishing means supplied with outputs of said first and third digital-to-analog converters;

second reference gain establishing means supplied with outputs of said second and fourth digital-to-analog converters; and

switching means for selectively switching over an incoming clock pulse, to supply said clock pulse to respective clock pulse input terminals of said first and second reversible counter means or said third and fourth reversible counter means,

said clock pulse input terminals of said first and second reversible counter means being respectively connected to load terminals of said third and fourth reversible counter means,

said first and second variable gain amplifying means respectively being supplied with gain varying control voltages from said first and second reference gain establishing means,

said matrixing means producing a luminance signal and two color difference signals.

2. An automatic white adjusting circuit for a television camera having a color image pick-up device generating an output signal from which first and second primary color signals and an other signal are derived, said other signal being either in a luminance signal or a third primary color signal, said automatic white adjusting circuit comprising:

first and second variable gain amplifying means for amplifying said first and second primary color signals, respectively;

matrixing means applied with said other signal and outputs of said first and second variable gain amplifying means, for producing first and second color difference signals;

first and second lowpass filters respectively applied with said first and second color difference signals;

means for generating reference levels equal to DC levels of said first and second color difference signals when picking up an image of a white object by said image pick-up device;

first and second comparing means respectively supplied with said reference levels to a single input terminal, and supplied with respective outputs of said first and second lowpass filters to their respective other input terminal;

first and third reversible counter means respectively supplied with an output of said first comparing means to their respective up/down input terminals;

second and fourth reversible counter means respectively supplied with an output of said second comparing means to their respective up/down input terminals;

switching means for selectively switching over an incoming clock pulse, to supply said clock pulse to respective clock pulse input terminals of said first and second reversible counter means or to respective clock pulse input terminals of said third and fourth reversible counter means;

said clock pulse input terminals of said first and second reversible counter means being respectively connected to load terminals of said third and fourth reversible counter means;

first, second, third, and fourth digital-to-analog converters respectively being supplied with parallel outputs of said first, second, third, and fourth reversible counter means; and

first and second reference gain establishing means respectively supplied with outputs of said first and third digital-to-analog converters and outputs of said second and fourth digital-to-analog converters, for respectively producing first and second gain control voltages to be respectively supplied to said first and second variable gain amplifying means.

3. An automatic white adjusting circuit as claimed in claim 2 in which said switching means first supplies said clock pulse to the respective clock pulse input terminals of said first and second reversible counter means and the respective load terminals of said third and fourth reversible counter means until said first and second reversible counter means respectively reach convergence states, and secondly cuts off said supply of said clock pulse to switch over said supply of said clock pulse to the respective clock pulse input terminals of said third and fourth reversible counter means until said third and fourth reversible counter means respectively reach convergence states, and cut off the latter supply of said clock pulse when said third and fourth reversible counters respectively reach said convergence states.

4. An automatic white adjusting circuit as claimed in claim 3 in which number of bits in said first, second, third, and fourth reversible counter means are substantially equal to each other, and initial counted values of said third and fourth reversible counter means are preset to values substantially half the maximum counted values which can be respectively obtained.

5. An automatic white adjusting circuit as claimed in claim 4 in which said third and fourth digital-to-analog converters are respectively constructed to obtain voltages of step forms in which voltage values per step are smaller than those of said first and second digital-to-analog converters.

6. An automatic white adjusting circuit as claimed in claim 5 in which said first and second primary color signals are red and blue color signals, respectively, and said other signal is a luminance signal.

7. An automatic white adjusting circuit as claimed in claim 5 in which said first and second primary color signals are red and blue color signals, respectively, and said other signals is a green color signal.

8. An automatic white adjusting circuit as claimed in claim 3 in which said switching means is an electronic switching circuit for selectively switching over said supply of said clock pulse.