Computer peripheral control apparatus

• US 4,486,826 A
• Filed: 10/01/1981
• Issued: 12/04/1984
• Est. Priority Date: 10/01/1981
• Status: Expired due to Term

• Current Assignee: Stratus Computer, Inc. (Stratus Technologies Bermuda Holdings Ltd.)
• Original Assignee: Stratus Computer, Inc. (Stratus Technologies Bermuda Holdings Ltd.)
• Inventors: Baty, Kurt F., Wolff, Kenneth T., Samson, Joseph E.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/307,524
• Time in Patent Office: 1,160 Days
• Field of Search: 371/67, 371/68, 371/69, 371/7, 371/8, 371/9, 371/10, 371/11, 364/200, 364/900
• US Class Current: 714/5.11
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1625 in communications, e.g. transmission, interfaces
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator

Abstract

A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.

Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.

The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Claims

1. Peripheral control apparatus for connection with a computer bus structure for the transfer of data between one or more computer functional units connected to that bus structure and at least one computer peripheral device connected with the control apparatus, where each functional unit is any of a central processing unit, a memory unit, and another peripheral control unit, and where the bus structure includes first and second duplicative buses, said apparatus having the improvement comprising

A. input means for receiving signals from any of said other functional units by way of any of said first and second buses and being conditioned by an applied control signal input thereto from said bus structure for responding to such signals on only a single one of said first and second buses,

B. bus output means for applying signals, for transfer to any of said other functional units, identically to both of said first and second buses independent of the conditioning of said input means,

C. device output means for connection to the peripheral device,

D. first and second device control means, each of which is connected with said input means to receive signals from said bus structure and is arranged for providing identical operations in response to said received signals and for producing output signals in response to said operations, and at least said first of which is arranged to apply output signals to said bus output means and to apply further output signals to said device output means, and

E. first fault-detecting means for detecting a first selected fault condition at least in signals transferred with respect to said device control means and responding to such a detected fault-condition to disable said bus output means from applying signals to either of said first and second buses.

2. In apparatus according to claim 1, the further improvement in which said first fault-detecting means detects a fault condition in signals applied to said buses by way of said output means.

3. In apparatus according to claim 2, the further improvement comprising further fault-detecting means for detecting a second selected fault-condition in signals transferred in at least one direction at said device output means.

4. In apparatus according to claim 3, the further improvement in which

A. said further fault-detecting means detects said second fault condition in signals applied to said device output means, and

B. said first fault-detecting means includes means for responding to the detection of said second fault condition for disabling said bus output means.

5. In apparatus according to claim 1 where the bus structure further includes a third bus, the further improvement comprising means for receiving signals from, and for applying signals to, the third bus, said means providing such signal receiving and signal applying operations both in the absence of any said detection fault condition and in the presence thereof.

6. In apparatus according to claim 1, the further improvement comprising means for identically applying to both said control means signals received at said device output means from a peripheral device.

7. In apparatus according to claim 1, the further improvement in which said first fault-detecting means includes comparator means for comparing signals output from said first control means to said buses by way of said bys output means with corresponding signals from said second control means.

8. In apparatus according to claim 1, the further improvement comprising means for comparing signals output from said first control means to the peripheral device by way of said device output means with corresponding signals from said second control means.

9. In apparatus according to claim 1, the further improvement comprising means for checking signals received at said device output means from a peripheral device for a fault condition, and for producing a fault-reporting signal in response thereto.