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Microprocessor apparatus

  • US 4,486,827 A
  • Filed: 01/18/1982
  • Issued: 12/04/1984
  • Est. Priority Date: 11/09/1979
  • Status: Expired due to Term
First Claim
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1. In a microprocessor product development system having a central processing unit and memory connected to a common bus, apparatus for using said central processor unit in both a user mode and a monitor mode while saving the user mode system state when switching to the monitor mode, comprising:

  • said central processor unit including address bus terminals connected to said common bus a plurality of digital logic device means, a first program counter means for storing the program address of a location of said memory, and means responsive to a clock signal for connecting the value of said program counter to said address bus terminals, andsaid central processor unit means further including means for resetting said first program counter means and said plurality of digital logic device means in response to a reset signal and for resetting only said first program counter means in response to a special reset signal having a different detectable characteristic from said reset signal, whereby the user mode system state is saved when said special reset signal is applied to the central processor unit to switch the system from the user mode to the monitor mode.

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