Incremental digital filter

• US 4,486,850 A
• Filed: 12/27/1976
• Issued: 12/04/1984
• Est. Priority Date: 11/11/1974
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/754,660
• Time in Patent Office: 2,899 Days
• Field of Search: 364/724, 364/725, 364/726, 364/727, 364/728, 364/747, 364/702, 364/604, 364/572, 364/576, 333/7, 324/77
• US Class Current: 708/494
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An incremental digital filter provides high speed and low cost capability such as for performing fast Fourier transforms (FFTs), correlations, convolutions, and other digital filter operations. One configuration operates at microwave sample rates, computing a complete 512-point FFT in 0.2 microseconds for an effective sample rate of 2.56 gigahertz. High speed and low cost are derived from a parallel pipeline architecture in combination with incremental processing. Parallel pipeline architecture provides extremely high speed while the incremental mechanization provides a simple arrangement with a low component count for low cost. The incremental nature of the processor provides an integrating type mechanization, where integration-after-transformation yields high processing gain for signal-to-noise-ratio enhancement.

High data rate input and output mechanizations are provided to accommodate the high processing rates. An improved input mechanization involves analog signal to incremental digital conversion. An improved output mechanization involves integration after filtering for data rate reductions and for signal enhancement and also involves a bus output structure for multiplexing of output parameters.

Claims

1. A data processing system comprising:

input means for generating at least one incremental time related input signal and

incremental Fourier transform processor means for generating an incremental frequency related processed signal in response to the incremental time related input signal.

3. The system as set forth in claim 1 above, wherein said processor means includes incremental complex multiplication means for generating the processed signal as a complex product in response to the incremental time related input signal.

4. The system as set forth in claim 1 above, further comprising:

transducer means for generating an analog input signal;

wherein said input means includes means for generating the incremental time related input signal in response to the analog input signal from said transducer means.

5. The system as set forth in claim 1 above, further comprising:

means for generating an analog input signal;

wherein said input means includes means for generating the incremental time related input signal as a binary digital signal in response to a threshold of the analog input signal.

6. The system as set forth in claim 1 above, wherein said processor means includes means for generating the incremental frequency related processed signal in response to the incremental time related input signal and a constant number.

7. The system as set forth in claim 1 above, wherein said processor means includes add means for generating an incremental sum signal in respone to the incremental incremental time related input signal and means for generating the incremental frequency related processed signal in response to the incremental input signal responsive sum signal.

8. The system as set forth in claim 1 above, wherein said processor means includes means for generating an incremental difference signal in response to the incremental time related input signal and means for generating the incremental frequency related processed signal in response to the incremental input signal responsive difference signal.

9. The system as set forth in claim 1 above, further comprising means for generating a whole number digital signal in response to the incremental frequency related processed signal, from said incremental Fourier transform processor means.

2. A data processing system comprising:

input means for generating at least one incremental time related input signal and

incremental fast Fourier transform processor means for performing a fast Fourier transform computation to generate an incremental frequency related processed signal in response to the incremental time related input signal.

10. A data processing system comprising:

input means for generating at least one incremental time related input signal and

incremental Fourier transform processor means for generating an incremental frequency related processed signal in response to the incremental time related input signal;

said incremental Fourier transform processor means including pipeline Fourier processor means for performing a pipeline Fourier processing computation to generate the incremental frequency related processed signal in response to the incremental time related input signal.

15. The system as set forth in claim 10 above, wherein said constant number storing means includes means for storing a whole number constant number and wherein said incremental product generating means includes means for generating the incremental product signal in response to the whole number constant number from said whole number constant number storing means and the incremental time related input signal from said input means.

11. A data processing system comprising:

input means for generating at least one incremental time related input signal and

incremental Fourier transform processor means for generating a frequency related processed number in response to the incremental time related input signal, said processor means including

a. means for storing a constant number;

b. means for storing the frequency related processed number;

c. means for generating at least one incremental product signal in response to an incremental product of the constant number from said constant number storing means and the incremental time related input signal from said input means; and

d. means for updating the frequency related processed number from said processed number storing means in response to the incremental product signal from said incremental product signal generating means.

12. The system as set forth in claim 11 above, wherein said constant number storing means includes register means for storing the constant number and loading means for loading the constant number into said register means.

13. The system as set forth in claim 11 above, wherein said constant number storing means includes wired constant means for storing a wired constant as a wired connection.

14. The system as set forth in claim 11 above, wherein said constant number storing means includes implicit constant number means for implying the stored constant number.

16. A data processing system comprising:

input means for generating at least one incremental time related input signal;

incremental Fourier transform processor means for generating at least one incremental frequency related processed signal in response to the incremental input signal; and

post processor means for generating at least one incremental post processed signal in response to the incremental frequency related processed signal from said incremental Fourier transform processor means.

17. The system as set forth in claim 16 above, further comprising means for generating a digital whole number signal in response to the incremental post processed signal from said post processor means.

18. A data processing system comprising:

input means for generating incremental time related input signal samples;

incremental Fourier transform processor means for generating incremental frequency related processed signal samples in response to the incremental input signal samples from said input means; and

coherent means for generating coherent whole number signal samples in respone to the incremental frequency related processed signal samples from said processor means.

19. A data processing system comprising:

input means for generating incremental time related input signal samples;

incremental Fourier transform processor means for generating incremental frequency related processed signal samples in response to the incremental input signal samples from said input means; and

noncoherent means for generating noncoherent whole number signal samples in response to the incremental frequency related processed signal samples from said processor means.

20. A digital data processing system comprising:

transducer means for generating analog transducer signals in response to sensed analog input signals;

signal processor means for generating processed analog signals in response to the analog transducer signals from said transducer means;

converter means for generating incremental input signals in response to the processed analog signals from said signal processor means;

transform processor means for generating frequency domain incremental signals in response to the incremental input signals from said converter means, said transform processor means including

a. butterfly processing circuits for generating butterfly incremental signals in response to the incremental input signals and

b. means for connecting said butterfly processing circuits to generate the frequency domain incremental signals in response to the incremental input signals from said converter means; and

output processor means for generating whole number digital output signals in response to the frequency domain incremental signals from said transform processor means.

21. The system as set forth in claim 20 above, wherein each of said butterfly processing circuits includes:

first incremental multiplication means for generating a first incremental product signal in response to a first one of the incremental input signals and a first whole number digital constant stored therein;

second incremental multiplication means for generating a second incremental product signal in response to a first one of the incremental input signals and a second whole number digital constant stored therein;

third incremental multiplication means for generating a third incremental product signal in response to a second one of the incremental input signals and the second whole number digital constant stored therein;

fourth incremental multiplication means for generating a fourth incremental product signal in response to the second one of the incremental input signals and the first whole number constant stored therein;

first incremental arithmetic means for generating a first incremental arithmetic signal in response to a difference between the first incremental product signal and the third incremental product signal;

second incremental arithmetic means for generating a second incremental arithmetic signal in response to a sum of the second incremental product signal and the fourth incremental product signal;

third incremental arithmetic means for generating a third incremental arithmetic signal in response to a sum of the first incremental arithmetic signal and a third one of the incremental input signals;

fourth incremental arithmetic means for generating a fourth incremental arithmetic signal in respone to a sum of the second incremental arithmetic signal and a fourth one of the incremental input signals;

fifth incremental arithmetic means for generating a fifth incremental arithmetic signal in response to a difference between the first incremental arithmetic signal and the third one of the incremental input signals; and

sixth incremental arithmetic means for generating a sixth incremental arithmetic signal in response to a difference between the second incremental arithmetic signal and the fourth one of the incremental input signals.

22. The system as set forth in claim 20 above, wherein said transducer means include an antenna for generating the analog transducer signals as microwave electrical signals in response to sensed analog input signals in the form of electromagnetic radiation.

23. The system as set forth in claim 20 above, wherein said transducer means includes microwave transducer means for generating the analog transducer signals as microwave analog transducer signals and wherein said signal processor means includes down converter means for generating the processed analog signals as down converted microwave signals in response to the microwave analog transducer signals from said microwave transducer means.

24. The system as set forth in claim 20 above, wherein said converter means includes a threshold detector for generating the incremental input signals in response to a threshold-related condition of the processed analog signals from said signal processor means.

25. The system as set forth in claim 20 above, wherein said transform processor means includes Fourier transform processor means for generating the frequency domain incremental signals in response to the incremental input signals from said converter means.

26. The system as set forth in claim 20 above, wherein said transform processor means includes discrete Fourier transform processor means for generating the frequency domain incremental signals in response to the incremental input signals from said converter means.

27. The system as set forth in claim 20 above, wherein said output processor means includes integration means for generating the whole number digital output signals in response to integration of the frequency domain incremental signals from said transform processor means.

28. The system as set forth in claim 20 above, further comprising integration means for generating integrated frequency domain whole number digital signals in response to the whole number digital output signals from said output processor means.

29. The system as set forth in claim 20 above, further comprising coherent integration means for generating coherent integrated signals in response to integration of the whole number digital output signals generated with said output processor means.

30. The system as set forth in claim 20 above, further comprising non-coherent integration means for generating non-coherent integrated signals in response to integration of the whole number digital output signals from said output processor means.

31. The system as set forth in claim 20 above, wherein said butterfly processing circuits include a plurality of digital differential circuits for generating the butterfly incremental signals in response to the incremental input signals.

32. The system as set forth in claim 20 above, wherein said transducer means includes an acoustical transducer for generating the analog transducer signals as acoustical signals in response to the sensed analog input signals in the form of acoustical input signals.

33. A filtering system comprising:

input means for generating a plurality of time domain signal samples;

filter means for generating a plurality of frequency domain signal samples in response to the time domain input signal samples; and

integrating means for generating a plurality of integrated signal samples in response to the frequency domain signal samples.

34. A filtering system comprising:

input means for generating a plurality of time domain signal samples;

Fourier transform means for generating a first plurality of Fourier transform frequency domain signal samples related to a first Fourier transform and a second plurality of Fourier transform frequency domain signal samples related to a second Fourier transform in response to the time domain signal samples from said input means; and

integrating means for summing each of a plurality of said first plurality of Fourier transform frequency domain signal samples with a related one of said second plurality of Fourier transform frequency domain signal samples to generate a plurality of integrated Fourier transform frequency domain signal samples.

35. A filtering system comprising:

input means for generating a plurality of incremental time domain signal samples;

incremental filter means for generating a plurality of incremental frequency domain signal samples in response to the incremental time domain input signal samples; and

integrating means for generating a plurality of integrated signal samples in response to the incremental frequency domain signal samples.

36. A filtering system comprising:

input means for generating incremental time related signal samples and

incremental processor means for generating incremental frequency related signal samples in response to the incremental time related signal samples.

37. A filtering system comprising:

input means for generating incremental time related signal samples and

incremental Fourier transform processor means for generating incremental frequency related signal samples in response to the incremental time related signal samples.

38. A filtering system comprising:

input means for generating time related signal samples;

incremental processor means for generating incremental frequency related signal samples in response to the incremental time related signal samples; and

integration means for generating whole number digital signal samples in response to the incremental frequency related signal samples.

39. A Fourier transform processor for generating Fourier transformed incremental output signals in response to incremental input signals, said Fourier transform processor comprising:

incremental means for incrementally generating the transformed incremental output signals in response to the incremental input signals and

integration means for generating digital whole number output signals in response to the incremental output signals.