Bidirectional source to source stacked FET gating circuit

• US 4,487,458 A
• Filed: 09/28/1982
• Issued: 12/11/1984
• Est. Priority Date: 09/28/1982
• Status: Expired due to Fees

• Current Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Janutka, William J.
• Primary Examiner(s): Anagnos, Larry N.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US06/425,196
• Time in Patent Office: 805 Days
• Field of Search: 307/241, 307/242, 307/570, 307/571, 307/572, 307/577, 307/582, 307/583, 307/584, 307/270, 307/304, 307/499, 307/501, 307/352, 307/353, 307/200 B, 357/23 GP
• US Class Current: 327/436
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

Stacked gating circuitry is provided for controlling a plurality of pairs of power FETs stacked in series, each pair being bidirectionally source to source connected for AC conduction. All the power FETs turn on from a single gate terminal through series connected current sources, one current source for each FET pair. The FETs turn on in ripple effect.

Claims

1. A bidirectional FET circuit comprising:

a plurality of pairs of enhancement mode power FETs, each pair comprising first and second FETs connected source to source in series relation, said pairs connected in series between first and second main power terminals, current conduction in one direction flowing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain PN junction of said second FET, and in the opposite direction through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain PN junction of said first FET; and

a plurality of gating circuits, one gating circuit for each said pair of power FETs for driving the latter into conduction, wherein said gating circuits are stacked in series for driving said pairs of power FETs sequentially into conduction from a single gate terminal.

2. A bidirectional FET circuit comprising:

a plurality of pairs of enhancement mode power FETs, each pair comprising first and second FETs connected source to source in series relation, said pairs connected in series between first and second main power terminals, current conduction in one direction flowing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain PN junction of said second FET, and in the opposite direction through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain PN junction of said first FET; and

a plurality of current sources connected in series, each current source connected to the gates of a respective said FET pair for driving the latter into conduction.

3. The invention according to claim 2 comprising a plurality of resistors one for each said power FET pair, each said resistor having one end connected to a node connecting the FET sources of its respective said pair, and having the other end connected to a node connecting its respective said current source and a node connecting the FET gates of its respective pair, such that the gate of source potential for each FET of each pair is the product of the current through the respective said resistor from the respective said current source and the resistance value of the respective said resistor, regardless of the polarity of the said main power terminals.

4. The invention according to claim 3 wherein said current sources are connected in series between a single gate terminal and the gates of the final said power FET pair.

5. The invention according to claim 4 wherein said current sources comprise a plurality of source followers FETs.

6. The invention according to claim 5 wherein:

said main power terminals are connectable across an AC power source, a load and ground;

said gate terminal is connectable to a source of gate voltage referenced to ground; and

said current source FETs comprise p-channel MOSFETs, each having a gate connected to ground, each having a drain connected to the source of the next successive current source FET and also connected to the gates of its respective said power FET pair, the source of the first said current source FET being connected to said gate terminal.

7. The invention according to claim 3 comprising a plurality of fast turn-off circuits, one for each said power FET pair, each fast turn-off circuit comprising transistor means biased into conduction by removal of gate drive and by residual stored charge in the gate to source capacitance of said FETs of its respective pair, said transistor means in a conductive state depleting said residual charge from said FET gates of its respective said pair.

8. The invention according to claim 7 wherein at least one said transistor means comprises a pair of regeneratively coupled bipolar transistors driven into latched conduction by the residual stored charge on said FET gates of its respective said pair in combination with the absence of gate current.

9. The invention according to claim 8 wherein said bipolar transistors comprise a first PNP transistor having its emitter connected to a node connecting said FET gates of its respective said pair and having its base connected to said respective current source, and an NPN transistor having its base connected to the collector of said PNP transistor, its collector connected to the base of said PNP transistor, and its emitter connected to said node connecting said FET sources of its respective said pair.

10. The invention according to claim 7 wherein said transistor means of said fast turn-off circuit comprises a pair of bipolar transistors connected in Darlinton relation between said node connecting said FET gates of its respective said pair and said node connecting said FET sources of its respective said pair, and having a base connected to said respective current source.

11. The invention according to claim 10 wherein said Darlington transistor pair comprises a first PNP transistor having its emitter connected to said node connecting said FET gates of its respective said pair and its collector connected to said node connecting said FET sources of its respective said pair, and a second PNP transistor having its emitter connected to the base of said first PNP transistor, its base connected to said respective current source, and its collector connected to said node connecting said FET sources of its respective said pair.

12. A three terminal bidirectional FET circuit comprising:

a plurality of pairs of enhancement mode power FETs, each pair comprising first and second FETs connected source to source in series relation, said pair connected in series between first and second main power terminals, current conduction in one direction flowing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain PN junction of said second FET, and in the opposite direction through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain PN junction of said first FET;

a plurality of gating FETs connected in series for successive turn-on, each said gating FET also connected to a respective one of said pairs of power FETs for like successive turn-on of the latter.

13. The invention according to claim 12 wherein each said gating FET is connected to each of the gates of said power FETs of its respective said pair and also connected through resistance means to a node connecting the sources of said power FETs of its respective said pair to establish the gate to source voltage of the latter for turn-on regardless of the polarity of said main power terminals.

14. The invention according to claim 12 wherein said gating FETs are connected in common gate configuration with their gates connected to a common reference voltage.