System for controlling data flow

• US 4,488,224 A
• Filed: 08/10/1982
• Issued: 12/11/1984
• Est. Priority Date: 08/10/1982
• Status: Expired due to Fees

• Current Assignee: IPL Systems, Inc. (Seagate Technology Holdings Plc)
• Original Assignee: IPL Systems, Inc. (Seagate Technology Holdings Plc)
• Inventors: Ippolito, Stephen J., Lambert, William J., Singer, Arthur L.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US06/406,775
• Time in Patent Office: 854 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/210
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields

Abstract

A control system is described for controlling the flow of multi-format, multi-bit macroinstructions for loading data into registers. The control system is adapted to: (A) control microprogram flow of instructions based on data within a floating point macroinstruction, (B) speed up macroinstruction flow as a function of data within various fields of the macroinstruction, and (C) speed up macroinstruction branches.

Claims

1. A system for generating a specification error signal in response to a predetermined type of instruction in at least one preselected format containing:

(i) an operation code of at least two binary bits of information, the binary state of at least one bit indicating said instruction is of said predetermined type, and (ii) at least one field of at least two binary bits of information the binary states of said two bits determining whether a specification exception exists in said instruction, said system comprising, in combination;

discriminator means for generating a first enabling signal in response to said instruction when said instruction is in said preselected format, said discriminator means comprising;

(1) means for detecting and discriminating between instructions in said preselected format and instructions in other formats, and (2) means for generating said first enabling signal when said instructions are in said preselected format;

means for generating a second enabling signal in response to the binary state of said one bit of said operation code indicating said instruction is of said predetermined type; and

means for generating said specification exception signal in response to (a) said first enabling signal, (b) said second enabling signal, and (c) a predetermined binary state of each of said bits of said field of said instruction.

2. a system according to claim 1, wherein said system includes means for generating said specification error signal in response to instructions of said predetermined type in at least two preselected formats, one of said preselected formats of said instruction including an operation code and at least one of said fields, and the other of said preselected formats of said instruction including an operation code and at least two of said fields, and further wherein:

(1) said discriminator means generates said first enabling signal in response to said instruction when said instruction is in either of said two preselected formats and said means for detecting discriminates between instructions of said two preselected formats and instructions of other formats, and (2) said means for generating said specification exception signal generates said specification exception signal responsively to;

(a) said first enabling signal, (b) said second enabling signal, and (c) a predetermined binary state of each of said bits of said one field of instruction when said instruction is in said one preselected format and a predetermined binary state of each of said bits of each of said two fields when said instruction is in said other preselected format.

3. A system according to claim 2, wherein the format of each said instruction is a function of the binary states of each of said two bits of said operation code of said instruction and said discriminator means includes a pair of input terminals for receiving said two bits of said operation code of each said instruction, means coupled to said pair of input terminals for detecting the binary state of each of said two bits, and means responsive to said two states for generating said first enabling signal when said instruction is in said one preselected format and said first enabling signal when said instruction is in said other preselected format.

4. A system according to claim 3, wherein said means for generating said specification exception signal includes means responsive to said one first enabling signal, said second enabling signal and said predetermined binary state of select bits of said one field when said instruction is in said one preselected format, and means responsive to said another first enabling signnal, said another enabling signal and said predetermined binary state of select bits of each of said two fields when said instruction is in said other preselected format.

5. A system for generating a plurality of binary bits of data adapted to be used for controlling the flow of information to a register, said plurality of bits of data being contained within at least one field of an instruction in at least four different formats and said register being cleared when the binary states of the bits of data within said field in at least some of said formats are each at a corresponding predetermined level, wherein:

(a) an instruction in each of said formats is of the type comprising an operation code including at least two binary bits of information, the combined binary states of the two bits being a function of the format of said instruction, and (b) the instructions of three of said formats each comprises at least one field of at least two binary bits of data and an instruction in the fourth of said formats comprises at least two fields each of at least two bits of data, said system comprising, in combination;

signal discriminator means responsive to said two bits of information of the operation code of an instruction for selectively generating at least four distinct format signals each as a function of a different combination of the binary states of the two bits of information of said operation code so as to represent a select and different one of said formats;

multiplexer means for transmitting;

(1) said plurality of bits of data within said one field of an instruction in a first one of said three formats in response to a first one of said format signals representative of one of said three formats;

(2) said plurality of bits of data within said first of said two fields of an instruction in said fourth format in response to either one of a first select signal and a second select signal;

(3) said plurality of bits of data within the second of said two fields of an instruction in said fourth format in response to the absence of each of said first format signals, said first select signal and said second select signal;

(4) said plurality of bits of data within said one field of an instruction in the second one of said three formats in response to the absence of each of the first format signal, first select signal and second select signal; and

(5) said plurality of bits of data within the one field of an instruction in the third one of said three formats in response to the absence of each of said first format signals, first select signal and second select signal;

decoding means responsive to the fourth format signal representative of an instruction in the fourth format for generating;

(1) a first clear signal for clearing said register when the bits of said data of each of said first and second fields of an instruction in the fourth format are each at said corresponding predetermined level,

(2) said first select signal when only the bits of said data of said first field of an instruction in said fourth format are each at said corresponding predetermined level; and

(3) said second select signal when at least one of the bits of said data of each of said first and second fields of an instruction in the fourth format differ from the corresponding predetermined level;

means responsive to the second format signal for generating a second clear signal so as to clear said register when the bits of said data of said one field of an instruction in said second format are each at said corresponding predetermined level; and

means responsive to the third format signal for generating a third clear signal so as to clear said register when the bits of said data of said one field of an instruction in said third format are each at said corresponding predetermined level.

6. A system according to claim 5, wherein an instruction in said third format includes a third select signal and a second field of at least two bits of data, said system further including second multiplexer means coupled between said first multiplexer means and said register for transmitting:

(1) said plurality of bits of said data within said second field of an instruction in said third format in response to said third select signal, and

(2) the output of said first multiplexer means in response to the absence of said third select signal.

7. A system according to claim 6, further including means responsive to said third format signal for generating a fourth clear signal so as to clear said register when the bits of said data of said second field of an instruction in said third format are each at a corresponding predetermined level.

8. A system according to claim 7, wherein an instruction in said third format includes two binary bit words transmitted sequentially with respect to one another, the first of said words containing the operation code and said first field, and the second of said words including said second field, said system further comprising means for preventing the generation of said third clear signal in response to said second word.

9. A system for generating an instruction initiation signal for initiating a first instruction operation and for blocking a second instruction operation in response to at least one instruction comprising:

(1) an operation code of a plurality of binary bits of information, each bit being at a predetermined binary level, and (2) at least one field of data comprising a plurality of binary bits, at least one of said bits providing a condition code when at a preselected binary level, said system comprising;

means for generating an enabling signal in response to said operation code when said plurality of binary bits of said operation code are each at its predetermined binary level;

means for generating a condition code input signal representative of the select one of said binary bits of said field;

multiplexer means responsive to said condition code input signal for selectively transmitting said select one of said binary bits, and

means for generating said instruction initiation signal for initiating said first instruction operation and for blocking said second instruction operation in response to;

(a) said enabling signal, and (b) said select one of said binary bits when said select one is at said preselected binary level.

10. A system according to claim 9, wherein said system includes means for generating said initiation signal in response to instructions of at least two different formats, each said instruction comprising said operation code and said one field, and further including means for generating a disabling signal when the plurality of bits of said field of an instruction of one format are each at a preselected binary level, wherein said multiplexer means is responsive to said disabling signal so as to prevent said select one of said binary bits from being transmitted.

11. A system according to claim 10, wherein each format of said instruction is defined by the binary state of at least one bit of said operation code, said means for generating said disabling signal includes means for detecting each of said plurality of bits of said field and for generating a first signal when said plurality of bits of said field are each at said preselected level, and means for detecting said one bit of said operation code and for generating a second signal when said instruction is in said one format.