Interface facility for a packet switching system

• US 4,488,289 A
• Filed: 06/25/1982
• Issued: 12/11/1984
• Est. Priority Date: 06/25/1982
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: AT&T, Inc.
• Inventors: Turner, Jonathan S.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/392,228
• Time in Patent Office: 900 Days
• Field of Search: 370/60, 370/92, 370/94, 370/93, 370/86
• US Class Current: 370/409
• CPC Class Codes: H04L 2012/5649 Cell delay or jitter
• CPC Class Codes: H04L 49/10 characterised by the switching fabric construction
• CPC Class Codes: H04L 49/112 Switch control, e.g. arbitration
• CPC Class Codes: H04L 49/118 Address processing within a device, e.g. using internal ID or tags for routing within a switch
• CPC Class Codes: H04L 49/1507 Distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/501 Overload detection
• CPC Class Codes: H04L 49/555 Error detection

Abstract

A communication method and packet switching system in which packets comprising logical addresses and voice/data information are communicated through the system by packet switching networks which are interconnected by high-speed digital trunks with each of the latter being directly terminated on both ends by trunk controllers. During initial call setup of a particular call, central processors associated with each network in the desired route store the necessary logical to physical address information in the controllers which perform all logical to physical address translations on packets of the call. Each network comprises stages of switching nodes which are responsive to the physical address associated with a packet by a controller to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols. Each packet has a field which is automatically updated by the controllers for accumulating the total time delay incurred by the packet in progressing through the networks. Each processor has the capability of doing fault detection and isolation on the associated network, trunks, and controllers by the transmission of a single test packet. The testing is done solely in response to the test packet and no preconditioning of controllers or networks is necessary.

Claims

1. A packet switching system for communicating a plurality of messages each comprising a plurality of packets, and each packet comprising a logical address, said system comprises:

transmission means for communicating a one of said messages;

a central processor responsive to destination information of a first packet of said one of said messages to generate logical and physical address information;

memory means associated with said transmission means responsive to the generated logical and physical address information to store said generated information;

controller means associated with said transmission means comprising means responsive to a subsequent one of said packets of said one of said messages to read the stored logical and physical address information, means for concatenating said logical and physical address information with said subsequent one of said packets, and means for transmitting said concatenated logical and physical address information and said subsequent one of said packets;

a switching network responsive to said transmitted concatenated logical and physical address information and said subsequent one of said packets to route said logical and physical address information and said subsequent one of said packets through said network.

2. A packet switching system for the transmission of a first type packets having logical address information and second type packets having switch address information and other logical address information and comprises an interface means interconnecting a switching network and transmission means, said interface means comprises:

memory means for storing said first type packets and other logical address information associated with switch address information;

addressing means responsive to a receipt of one of said first type packets to effect the storage of the received packet in said memory means;

said addressing means further comprising means for reading the stored one of said first packets and means responsive to said logical address information in said one of said first type packet for reading associated other logical and switch address information from said memory means; and

transmitter means responsive to the read other logical and switch address information and the read one of said first type packets for forming one of said second type packets.

3. The invention of claim 2 wherein said interface means further comprises receiver means responsive to a second one of said second type packets from said switching network to effect a formation of a second one of said first type packets from said second one of said second type packets;

said addressing means further comprising means responsive to the formed second one of said first type packets for storing said second one of said first type packets in said memory means;

said interface means further comprising transmit means responsive to said storage of the second one of said first type packets for transmitting said second one of said first type packets on said transmission means.

4. The invention of claim 3 wherein said memory means comprises a buffer having a plurality of memory locations;

said addressing means further comprises means for monitoring said buffer for determining the availability of ones of said memory locations for storing packets in said buffer and means for detecting said one of said first type of packets in said buffer;

interface means further comprises receive means for receiving said one of said first type packets via said transmission means and said receive means comprising means controlled by said monitoring means for operating said addressing means to effect a storage of said one of said first type packets into said locations of said buffer;

said transmitter means further comprises output means controlled by said detecting means to effect the communication of said one of said first type packets from said buffer to said switching network.

5. The invention of claim 4 wherein each of said second type packets comprises an address field for storing the switch address information and a length field for storing the length information of said second type packets;

and

said receive means further comprises means responsive to said one of said first type packets to allocate the memory locations in said buffer to store said address information and said length information of said first one of said second type packets.

6. The invention of claim 5 wherein said receive means further comprises:

means responsive to said first one of said first type packets for counting the number of bits contained in said first one of said first type packets and means for storing said count plus a prescribed number of bits for said address field and said length field of said first one of said second type packets.

7. The invention of claim 6 wherein said monitoring means further comprises a first counter to generate addresses for writing into said buffer, a second counter to generate addresses for reading information from said buffer and comparing means for comparing said first and said second counters, and means responsive to the availability of memory locations in said buffer to transmit a first signal to said receive means;

said receive means further comprising means responsive to said first one of said first type packets to transmit a third signal to said monitoring means;

said detecting means further comprises a storage means responsive to said third signal to be activated to a first state and means for transmitting a second signal to said output means to effect the reading of said one packet of said first type packets from said buffer by said second counter upon said first and second counters not being equal.

8. The invention of claim 7 wherein said monitoring means further comprises a third counter indicating the address of the most significant memory location in said buffer and a comparator for comparing said first and third counter;

said monitoring means controlled by said comparator detecting said counter not equal to said third counter to withdraw said first signal signaling that storage of another packet in said buffer is precluded.

9. The invention of claim 7 wherein said detecting means further comprises means responsive to said first counter equaling said second counter to cause said storage means to be activated to a second state for effecting the withdraw of said transmission of said second signal to said output means signaling the unavailability of another one of said first type packets.

10. The invention of claim 9 wherein said addressing means further comprises a fourth counter;

said addressing means further comprising means responsive to said receipt of said first one of said first type packets in said receive means to set said fourth counter equal to said first counter;

said first counter responsive to said first one of said first type packets to control the storage of said first one of said first type packets by generating addresses to address said memory means;

said receive means further comprises means responsive to an error in said first one of said first type packets to set said first counter equal to said fourth counter.

11. The invention of claim 4 wherein said interface means further comprises receiver means for receiving said second type packets from said network;

said memory means further comprises a switch buffer;

said addressing means responsive to the receipt of a second one of said second type packets in said receiver means for storing said second one of said second type packets into said switch buffer;

said transmit means responsive to said second one of said second type packets stored in said switch buffer to communicating said stored packet on said transmission means.

12. The invention of claim 2 wherein a second one of said first type packets further comprises a function field;

said interface means further comprises transmit means;

said memory means comprises a buffer having a plurality of memory locations;

said receive means is further responsive to signals representing a first state in said function field to store said second one of said first type packets in said buffer; and

said transmit means further comprising means responsive to said first state in said function field for communicating said second one of said first type packets on said transmission means.

13. The invention of claim 12 wherein said receive means further comprises means responsive to said signals representing said first state in said second one of said first type packets and to transmit a first signal to said transmit means;

and

said transmit means further comprises means responsive to said first signal for reading from said buffer and means for transmitting said second one of said first type packets on said transmission means.

14. The invention of claim 2 wherein a second one of said second type packets comprises a control field;

and

said interface means responsive to signals representing a first state in said control field to transmit said second one of said second type packets back to said network.

15. The invention of claim 14 wherein said memory means comprises a buffer having a plurality of memory locations and said interface means further comprises:

said receiver means responsive to said second one of said second type packets from said network and said signals representing said first state to effect the storage of said second one of said second type packets in said buffer and comprises means to transmit a first signal to said transmitter means for effecting the transmission of said stored second one of said second type packets to said network.

16. The invention of claim 4 wherein said first one of said second type packet further comprises an address field for storing the switch address to route said first one of said second type packets through said network and a logical address field for storing the logical address information;

and

said transmitter means further comprises means responsive to said second signal and said logical address in said first one of said second type packets to effect the reading of said switch address information associated with said logical address from said memory means and means for storing said switch address information in said first one of said second type packet.

17. The invention of claim 16 wherein said first one of said second type packets is assembled from said memory means serially with said switch address field first followed by said logical address field, said transmitter means further comprises:

a shift register means for storing said switch address field and said logical address field;

second means for reading said logical address information from said logical address field;

third means for effecting a reading of the associated switch address information from said memory means in response to said logical address information;

fourth means for inserting the switch address information into the switch address field stored in said shift register means; and

fifth means for transmitting said first one of said second type packets from said shift register means by inserting new portions of said first one of said second type packets into said shift register means from said memory means.

18. The invention of claim 17 wherein said addressing means further comprises a first counter to address said switch address information associated with the logical address field of said first one of said first type packets;

said third means of said transmitter means further responsive to said logical address field being stored in said shift register means for storing the contents of said logical address field in said first counter; and

said first counter being responsive to said logical address field to address said memory means with said contents of said logical address field.

19. The invention of claim 2 wherein said packet switching system further comprises a central processor associated with said network;

said memory means further comprises a buffer;

said interface means further comprises a receiver means;

said processor comprising means for generating a second one of said second type packets having a data field containing logical address information and associated switch address information and a physical address designating the locations in said memory means where said logical address information and said associated switch address information are to be stored, and means for transmitting said seond one of said second type packets to said receiver means; and

said receiver means responsive to said second one of said second type packets to store said associated switch information and said other logical address information at the location in said memory means designated by said physical address information and the remainder of said second one of said second type packets in said buffer.

20. The invention of claim 19 wherein said transmitter means further comprises means responsive to said second one of said second type packets for reading said stored remainder of said second one of said second type packets and said stored switch address information and other logical address information, and means for transmitting a third one of said second type packets comprising the read information to said processor via said network.

21. The invention of claim 19 wherein said addressing means comprises a first counter for storing said physical address and a second counter for addressing said buffer;

and

said addressing means further comprising means responsive to said second one of said second type packets for storing said switch address and logical address information in memory locations of said memory means designated by said first counter and the remainder of said second one of said second type packets in said buffer designated by said second counter.

22. The invention of claim 21 wherein said receiver means further comprises means for transmitting a signal to said transmitter means after storing said second one of said second type packets in said memory means;

and

said transmitter means further comprises means responsive to said signal to read said second one of said second type packets from said second buffer and said memory locations designated by said physical address and means for forming said third one of said second type packets.

23. A packet switching system for communicating messages each comprising a plurality of packets, and each of said packets comprising logical address information and said system comprises:

a central processor;

a first interface facility responsive to the receipt of a first one of said plurality of packets of one of said messages to transmit said received packet to said central processor via said switching network;

said received packet comprises identification information;

a second interface facility;

said central processor responsive to said identification information of said received packet to generate logical and switch address information for transmission to said first interface facility;

said first interface facility further comprising means responsive to said logical and switch address information to store said logical and switch address information;

said first interface facility further comprising means responsive to a subsequent one of said packets of said one of said messages to access said stored logical and switch address information and means for concatenating said logical and switch address information with said subsequent one of said packets for transmission of said concatenated information to said switching network; and

said switching network responsive to said switch address information in said concatenated information to route said concatenated information to said second interface facility.

24. A switching system for communicating packets each having a field for storing address information, said system comprises:

transmission means;

a switching network;

interface means for interconnecting said transmission means and said network;

said interface means comprising memory means for storing logical address information associated with switch address information and operable for storing said packets received from said transmission means;

said interface means further comprising means responsive to the receipt of one of said packets from transmission means for controlling the storage of said one of said packets in said memory means; and

said interface means further comprising means for reading the stored one of said packets from memory, means for reading said logical address information associated with said switch information from said memory means, and means responsive to the read one of said packets to concatenate said read packet and said logical address information and said switch address information for transmission of said concatenated information to said switching network.

25. A packet switching system comprises a plurality of networks interconnected by a plurality of transmission means with each of said transmission means being connected to a one of said networks by one of a plurality of interface facilities, first type packets are transmitted on said plurality of transmission means and second type packets are transmitted within said networks, each of said type of packets comprising a function field, each of said interface facilities further comprises:

receiving means responsive to said function field of one of said first type packets containing signals representing a first state to effect a transmission of said one of said first type packets on said connected transmission means;

said receive means comprises means responsive to said function field of said one of said first type packets containing signals representing a second state to effect the transformation of said one of said first type packets into one of said second type packets and means for communicating said one of said second type packets to said connected network;

receiver means responsive to the function field of a second one of said second type packets from said network containing signals representing a first state to effect the transmission to said network of second one of said second type packet with said function field equal to said first state; and

said receiver means comprises means responsive to the function field of a third one of said second type packets containing signals representing a second state to effect the transformation of said third one of said second type packets to a second one of said first type packets and means for transmitting said second one of said first type packets to said transmission means.

26. A packet switching system for communicating a plurality of messages each comprising a plurality of packets, each of said packets comprising logical address and data, said system comprising:

processor means responsive to a receipt of identification data of one of said packets of one of said messages for generating logical address information and physical address translation information;

switching network means for switching other packets of said one of said messages to a destination;

distributed controller means for communicating said other packets of said one of said messages to said network means and comprising

means for storing the logical address information and the physical address translation information generated by said processor means; and

means responsive to a receipt of one of said other packets for concatenating the stored logical address information and the physical address information in said storing means with said one of said other packets.

27. The invention of claim 26 wherein said one of said packets comprises a call set-up packet, and

said controller means comprises means responsive to a receipt of said call set-up packet for controlling the switching of said set-up packet through said network means to said processor means.

28. The invention of claim 26 wherein said processor means is further responsive to said logical address signals of said one of said packets for producing logical address data and physical address translation data, and

further comprising another distributed controller means for communicating said other packets to said destination and received message packets from said destination to said first-mentioned controller means, and comprising

means for storing the logical address and physical address data produced by said processor means.

29. The invention of claim 28 wherein

said other distributed controller means comprises means responsive to a receipt of said message packets for communication to said first-mentioned distributed controller means for concatenating said message packets with the stored logical address and physical address data in said storing means of said other distributed controller means.

30. A method of communicating packets through a packet switching system comprising switching networks interconnected by a plurality of transmission means with each transmission means being connected to a given network by one of a plurality of interface facilities, first type packets comprising logical addresses are transmitted via said transmission means and second type packets comprising network addresses are transmitted within said networks, each of said switching network comprising switching elements responsive to the network addresses of said second type packets to route said second type packets to destination ones of said interface facilities, said method comprising the steps:

translating the logical address contained in one of said first type packets to the corresponding network address and another logical address upon a receipt of said one of said first type packets by one of said interface facilities from associated transmission means;

assembling one of said second type packets by concatenating said network address and said one of said first type packets;

replacing said logical address with said other logical address in said one of said first type of packets;

and

transmitting said one of said second type packets to said destination interface facility via said network.

31. The invention of claim 30 wherein each of said interface facilities further comprises external means for receiving and transmitting said first type packets, switch means for receiving and transmitting said second type packets, and a memory means for storing said first type packets and for storing other logical address information associated with network address information, and further comprising the steps:

transforming said one of said second type packets to a second one of said first type packets upon a receipt of said one of said second type packets by said switch means of said destination interface facility;

storing said second one of said first type packets in said memory means in response to said second one of said first type packets; and

transmitting said second one of said first type packets by said external means of said destination interface facility on the associated transmission means.

32. The invention of claim 31 wherein said memory means comprises a buffer comprising a plurality of memory locations and said step of storing said first one of said first type packets in said memory means further comprises the steps of detecting that said buffer can store another packet;

transmitting to said switch means of said destination interface facilities a first signal indicating that said buffer can store another packet;

storing said first one of said first type packets in said buffer by said switch means of said destination interface facility in response to said first signal;

detecting that said buffer contains said first one of said first type packets;

transmitting a second signal to said external means of said destination interface facility; and

assembling said second one of said first type packets from said first one of said first type packet in said buffer by said external means of said destination interface facility in response to said second signal.

33. The invention of claim 30 wherein said one of said interface facilities further comprises an external means for receiving and transmitting said first type packets via said associated transmission means, switch interface means for receiving and transmitting said second type packets via said network, and a memory means for storing said first type packets and for storing other logical address information associated with switch address information, said first one of said second type packets comprises a length field for storing the length of said first one of said second packets and an address field for storing the switch address, said memory means further comprises a buffer for storing said first one of said first type packets, and further comprising the step of providing memory locations in said buffer for said first one of said first type packets and said length and address field of said first one of said second type packets.

34. The invention of claim 33 wherein said step of providing said length field further comprises the steps of calculating the number of bits contained in said first one of said second type packets;

and

storing the number representing the calculated number of bits in said first one of said first type packets plus the number of bits in said address field and said length field contained in said first one of said second type packets stored in said buffer.

35. The invention of claim 31 wherein said method further comprises the step of generating the address of the last packet read from said buffer;

calculating the address into which said first one of said first type packets was written into said buffer;

comparing said reading address with said writing address; and

generating said second signal upon said addresses not being equal.

36. The invention of claim 32 wherein said step of generating said first signal further comprising the step of generating the most significant memory location in said buffer;

comparing said most significant address with said storage address; and

generating and transmitting said first signal upon said most significant address and said storage address not being equal.

37. The invention of claim 36 wherein said step of storing said first one of said first type packets into said buffer further comprises the step of storing said generated storage address as a temporary address;

detecting an error in said first one of said first type packets; and

setting said storage address equal to said temporary address in response to said error.