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Merged-transistor switch with extra P-type region

  • US 4,489,341 A
  • Filed: 09/27/1982
  • Issued: 12/18/1984
  • Est. Priority Date: 09/27/1982
  • Status: Expired due to Term
First Claim
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1. A merged-transistor switch of the kind including a P-type silicon substrate (46) having an N-type epitaxial pocket (41), a double-diffused-vertical NPN transistor (40) formed in said epitaxial pocket (41) which serves as the NPN transistor collector, and including in said epitaxial pocket (41) an input P-MOS transistor (49) comprised of a P-type source region (50) formed in said epitaxial pocket (41) adjacent and spaced from a portion of the P-type base region (42) of said NPN transistor (40), and a metal gate (52) over the gap between said P-type source region (50) and base region (42), said NPN base region (42) serving as the drain of said P-MOS transistor (49), wherein the improvement comprises:

  • a third P-type region (68) formed in said epitaxial pocket (41) adjacent and spaced from another portion of said P-type base region (42) to form a lateral PNP transistor (64) therewith, in said N-type epitaxial pocket (41) and one metal layer (58) contacting both the emitter of said NPN transistor (40) and said third P-type region (68).

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