Merged-transistor switch with extra P-type region
First Claim
1. A merged-transistor switch of the kind including a P-type silicon substrate (46) having an N-type epitaxial pocket (41), a double-diffused-vertical NPN transistor (40) formed in said epitaxial pocket (41) which serves as the NPN transistor collector, and including in said epitaxial pocket (41) an input P-MOS transistor (49) comprised of a P-type source region (50) formed in said epitaxial pocket (41) adjacent and spaced from a portion of the P-type base region (42) of said NPN transistor (40), and a metal gate (52) over the gap between said P-type source region (50) and base region (42), said NPN base region (42) serving as the drain of said P-MOS transistor (49), wherein the improvement comprises:
- a third P-type region (68) formed in said epitaxial pocket (41) adjacent and spaced from another portion of said P-type base region (42) to form a lateral PNP transistor (64) therewith, in said N-type epitaxial pocket (41) and one metal layer (58) contacting both the emitter of said NPN transistor (40) and said third P-type region (68).
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Accused Products
Abstract
In one N-type epitaxial pocket of an integrated circuit there is formed a vertical NPN transistor and two other P-type regions each positioned adjacent but spaced from the P-type base region of the NPN. A metal gate over the gap between the base and one of the other P-type regions forms a high input-impedance P-MOS stage driving the NPN. A metal layer contacts both the NPN emitter and the PNP emitter formed by the third P-type region. This PNP transistor clamps the NPN collector-emitter to a safe voltage when switching an inductive load, and in a particularly efficient manner. A second P-MOS transistor is formed by extending the metal layer over the gap between the NPN-base and the third P-type region which transistor is capable of preventing leakage current out of the input P-MOS transistor in the off state form turning on the NPN transistor.
20 Citations
10 Claims
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1. A merged-transistor switch of the kind including a P-type silicon substrate (46) having an N-type epitaxial pocket (41), a double-diffused-vertical NPN transistor (40) formed in said epitaxial pocket (41) which serves as the NPN transistor collector, and including in said epitaxial pocket (41) an input P-MOS transistor (49) comprised of a P-type source region (50) formed in said epitaxial pocket (41) adjacent and spaced from a portion of the P-type base region (42) of said NPN transistor (40), and a metal gate (52) over the gap between said P-type source region (50) and base region (42), said NPN base region (42) serving as the drain of said P-MOS transistor (49), wherein the improvement comprises:
a third P-type region (68) formed in said epitaxial pocket (41) adjacent and spaced from another portion of said P-type base region (42) to form a lateral PNP transistor (64) therewith, in said N-type epitaxial pocket (41) and one metal layer (58) contacting both the emitter of said NPN transistor (40) and said third P-type region (68). - View Dependent Claims (2, 3, 4, 5, 6)
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7. A merged-transistor switch comprising:
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(a) a P-type silicon substrate; (b) an electrically isolated epitaxial silicon pocket of N-type formed in said substrate; (c) a silicon dioxide layer overlying the surface of said pocket; (d) a vertical NPN transistor, wherein said epitaxial pocket serves as the collector, and having a P-type base region formed in said epitaxial pocket and at least one emitter region of N-type formed in said base region; (e) a second P-type region in said epitaxial pocket adjacent but spaced from a portion of the edge of said NPN-base region; (f) a first metal gate overlying and spaced from the surface of said epitaxial pocket by said silicon dioxide layer, said metal layer and a thinned portion of said oxide layer extending over the gap between said second P-type region and said P-type-NPN-base region, to form a first P-MOS transistor; (g) a third P-type region in said epitaxial pocket adjacent but spaced from another edge portion of said NPN-base region; and (h) a metal film contacting said P-type base region of said NPN transistor and said third P-type region forming a PNP transistor having an emitter connected electrically via said metal film to said N-type emitter region of said NPN transistor. - View Dependent Claims (8, 9, 10)
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Specification