Process for producing a three-dimensional semiconductor device

• US 4,489,478 A
• Filed: 09/28/1982
• Issued: 12/25/1984
• Est. Priority Date: 09/29/1981
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sakurai, Junji
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Schiavelli, Alan E.
• Application Number:
  US06/425,644
• Time in Patent Office: 819 Days
• Field of Search: 29/574, 29/577 C, 29/571, 29/576 B, 148/1.5
• US Class Current: 438/18
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

At present, the majority of semiconductor devices are two-dimensional large-scale integration (LSI) semiconductor devices in which the semiconductor elements are arranged in a semiconductor layer in a two-dimensional manner. An aim of the techniques of production of semiconductor devices is to achieve, in the future, a super high integration amounting to 16 M bits or more per chip. For attaining such a super high integration, a multilayer semiconductor device must be produced. A method for producing a three-dimensional LSI semiconductor device prevents wasteful formation of semiconductor layers and insulating films. The method includes the step of forming, in a first semiconductor layer, a monitoring device for evaluating the circuit function of the semiconductor elements in the first semiconductor layer and subsequently forming another semiconductor layer above the first semiconductor layer. A preferred embodiment also includes the steps of: forming the impurity regions of the semiconductor elements by ion implantation; activating the implanted impurity ions by energy beam irradiation; and forming the insulating material regions of the semiconductor elements by high-pressure oxidation, or by low-temperature sputtering.

Claims

1. A process for producing a semiconductor device comprising a substrate, first and second semiconductor layers formed on the substrate, and an insulating film formed between the first and second semiconductor layers for insulating the first and second semiconductor layers from one another, the process comprising the steps of:

(a) preparing the substrate;

(b) forming the first semiconductor layer on the substrate;

(c) forming a first group of circuit elements, including a plurality of first semiconductor elements, in the first semiconductor layer;

(d) forming a first monitoring device, for monitoring the properties of the first group of circuit elements, on the first semiconductor layer;

(e) measuring the properties of the first monitoring device, thereby evaluating a circuit function of the first semiconductor elements;

(f) forming the insulating film on the first semiconductor layer;

(g) forming the second semiconductor layer on the insulating film;

(h) forming a second group of circuit elements, including a plurality of second semiconductor elements, in the second semiconductor layer;

(i) forming a second monitoring device on the second semiconductor layer;

(j) forming a conductor, extending through the insulating film, for electrically connecting the first monitoring device in the first semiconductor layer with the upper surface of the second semiconductor layer; and

(k) measuring the properties of the first monitoring device via the conductor.

2. A process according to claim 1, wherein said measuring step (d) is performed before said forming step (f).

3. A process according to claim 1, further comprising the steps of:

forming a plurality of chips on the first layer in the form of a matrix; and

forming the first monitoring device in at least one of the plurality of chips.

4. A process according to claim 1, further comprising the steps of:

forming a plurality of chips on the first layer in the form of a matrix;

forming vertical and horizontal scribe lines between the chips; and

forming the first monitoring device on a selected portion of the scribe lines.

5. A process according to claim 1, wherein said steps (c) and (h) each comprise the substeps of:

forming impurity regions in the first and second semiconductor elements by means of ion implantation; and

activating the implanted impurity ions by irradiation with an energy beam, and wherein said step (f) comprises forming the insulating film on the first semiconductor elements by means of high-pressure oxidation.

6. A process according to claim 1, wherein said steps (c) and (h) each comprise the substeps of:

forming impurity regions in the first and second semiconductor elements by means of ion implanation; and

activating the implanted impurity ions by irradiation with an energy beam, and wherein said step (f) comprises forming an oxide film, as the insulating film on the first semiconductor elements, by means of low-temperature sputtering.

7. A process according to claim 5 or 6, whereing the first semiconductor layer has a single crystalline portion, further comprising the steps of:

selectively removing and partly exposing the insulating film so as to expose the single crystalline portion of the first semiconductor layer;

forming a polycrystalline semiconductor layer on the insulating film; and

carrying out single crystallization of the polycrystalline semiconductor layer, using as a nucleus the single crystalline portion of the first semiconductor layer, by selectively irradiating selected portions of the polycrystalline semiconductor layer with an energy beam.

8. A process according to claim 3 or 4, wherein each of the plurality of chips has side surfaces, further comprising the steps of:

partly exposing the side surface of the plurality of chips; and

heating the plurality of chips in a hydrogen atmosphere.

9. A process for producing a semiconductor device having a substrate, comprising the steps of:

(a) forming a first semiconductor layer on the substrate;

(b) forming a first group of circuit elements, including first semiconductor elements, in the first semiconductor layer;

(c) forming a first monitoring device, for monitoring the first group of circuit elements, on the first semiconductor layer;

(d) forming a first insulating layer on the first semiconductor layer;

(e) forming a second conductor layer on the first insulating layer;

(f) forming a second group of circuit elements, including second semiconductor elements, in the semiconductor layer;

(g) forming a second monitoring device, for monitoring the second group of circuit elements, on the second semiconductor layer;

(h) forming a conductor, extending through the insulating layer, for electrically connecting the first monitoring device to the upper surface of the second semiconductor layer; and

(i) measuring the properties of the first monitoring device via the conductor.