Packet error rate measurements by distributed controllers

• US 4,490,817 A
• Filed: 12/13/1982
• Issued: 12/25/1984
• Est. Priority Date: 12/13/1982
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: AT&T, Inc.
• Inventors: Turner, Jonathan S.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/449,553
• Time in Patent Office: 743 Days
• Field of Search: 370/13, 370/17, 370/94, 370/60, 370/58, 371/5, 179/175.2 R, 179/175.3 A, 179/175.3 F
• US Class Current: 370/244
• CPC Class Codes: H04L 1/0083 Formatting with frames or packets; Protocol or part of protocol for error control
• CPC Class Codes: H04L 1/24 Testing correct operation
• CPC Class Codes: H04L 49/10 characterised by the switching fabric construction
• CPC Class Codes: H04L 49/112 Switch control, e.g. arbitration
• CPC Class Codes: H04L 49/118 Address processing within a device, e.g. using internal ID or tags for routing within a switch
• CPC Class Codes: H04L 49/1507 Distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/501 Overload detection
• CPC Class Codes: H04L 49/555 Error detection

Abstract

A trunk controller and processor arrangement for monitoring the error rate occurring in packets received from a high speed trunk. Within a packet switching system, packets comprising logical addresses, and voice/data information are communicated through the system by packet switching networks which are interconnected by high speed digital trunks with each of the latter being directly terminated on both ends by trunk controllers. During initial call setup of a particular call, central processors associated with each network in the desired route store the necessary logical to physical address information in the controllers which perform all logical to physical address translation on subsequent packets of the call. Each network comprises stages of switching nodes which are responsive to the physical address associated with a packet by a controller to communicate that packet to a designated subsequent node. Each trunk controller has an error rate monitoring circuit for measuring the error rate occurring in packets during transmission over the attached trunk. The error rate circuit notifies the associated processor when error rate excursions increase or decrease in excess of a multitude of processor specified percentages of error rate.

Claims

1. An error monitoring arrangement for measuring the rate of errors occurring in the transmission of packets, comprises:

means for generating error signals upon detection of errors in ones of said packets;

means responsive to said error signals for calculating present error signals representing an error rate;

means for generating a control signal upon receipt of a predetermined number of packets;

means for storing reference error signals;

means cooperating with said calculating means and said storing means for defining error rate thresholds; and

means cooperating with said defining means, said calculating means, and said storing means in response to said control signal for indicating error rate excursions beyond said thresholds by said present error signals from said reference error signals.

2. The error monitoring arrangement in accordance with claim 1 wherein said means for generating said control signal comprises:

means responsive to each of said packets for generating packet present signals;

a counter circuit decremented in response to said packet present signals for counting said predetermined number of packets;

means responsive to said counter circuit decrementing to zero for generating said control signal indicating the receipt of said predetermined number of packets;

constant register means for storing signals representing said predetermined number of packets; and

means responsive to said control signal for transferring the contents of said constant register means to said counter circuit to initialize said counter circuit for calculation of said predetermined number of packets.

3. The error monitoring arrangement in accordance with claim 1 wherein said calculating means comprises accumulator means responsive to said error signals for generating said present error signals;

and

means for operating said calculating means upon said predetermined number of packets being received for effecting a predetermined division of said present error signals.

4. The error monitoring arrangement in accordance with claim 1 wherein said defining means comprises:

mask register means for storing a plurality of mask signals;

mask circuit means responsive to said present error signals, reference error signals, and stored mask signals for logically generating a first and a second sets of mask output signals;

said indicating means comprising means for comparing said sets of mask output signals to indicate said error rate excursions upon said sets of mask output signals not being equal.

5. An error monitoring arrangement for measuring the rate of errors occurring in the transmission of packets, and comprises:

means for generating error signals upon receipt of incorrect ones of said packets;

means for generating valid packet signals upon receipt of correct ones of said packets;

means responsive to said valid packet signals and said error signals for generating a control signal upon a receipt of a predetermined number of packets;

means responsive to said error signals for calculating a first set of signals representing the error rate occurring in said predetermined number of packets;

means for storing a second set of signals representing a reference error rate; and

means responsive to subsets of signals representing said first and second sets of signals and said control signal for generating a report signal indicating excursions of said calculated error rate from said reference error rate.

6. The error monitoring arrangement in accordance with claim 5 wherein said subsets of signals comprise a first and second subsets of signals and said means for generating said report signal comprising means responsive to said control signal for selecting from said first and second sets of signals said first and second subsets of signals, respectively.

7. The error monitoring arrangement in accordance with claim 6 wherein said selecting means comprises a mask register for storing a set of mask signals representing a plurality of predetermined excursions;

mask circuit means responsive to said first and second sets of signals and stored mask signals of said mask register for logically generating said first and second subsets of signals; and

comparator circuit means responsive to said last mentioned signals for generating said report signal upon said subsets of signals not being equal.

8. The error monitoring arrangement in accordance with claim 5 wherein said calculating means comprises accumulator means incremented by one in response to each of said error signals for calculating the number of incorrect packets for said predetermined number of packets;

and

a present error register responsive to said control signal to store the most significant signals of said accumulator means for generating said first set of signals.

9. The error monitoring arrangement in accordance with claim 8 wherein said accumulator means further comprises means responsive to said control signal for effecting a predetermined division of the contents of said accumulator means.

10. The error monitoring arrangement in accordance with claim 5 wherein said means for generating said control signal comprises means responsive to said error signals and said valid packet signals for generating packet present signals;

a counter circuit decremented in response to said packet present signals for counting said predetermined number of packets;

means responsive to said counter circuit decrementing to zero for generating said control signal indicating the receipt of said predetermined number of packets;

constant register means for storing signals representing said predetermined number of packets; and

means responsive to said control signal for transferring the contents of said constant register means to said counter circuit to initialize said counter circuit for counting of said predetermined number of packets.

11. A packet switching system for communicating a plurality of packets having a packet switching network, transmission means and interface means interconnecting said transmission means and said switching network, said interface means comprises:

means for generating error signals upon receipt of incorrect ones of said packets;

means for generating valid packet signals upon receipt of correct ones of said packets;

means responsive to said valid packet signals and said error signals for generating a control signal upon a receipt of a predetermined number of packets;

means responsive to said error signals for calculating a first set of signals representing the error rate occurring in said predetermined number of packets;

means for storing a second set of signals representing a reference error rate;

means responsive to subsets of signals representing said first and second sets of signals and said control signal for generating a report signal indicating excursions of the calculated error rate from said reference error rate.

12. The interface means in accordance with claim 11 wherein said subsets of signals comprise a first and a second subsets of signals and said means for generating said report signal comprises means responsive to said control signal for selecting from said first and second sets of signals said first and second subsets of signals, respectively.

13. The interface means in accordance with claim 12 wherein said selecting means comprises a mask register for storing a set of mask signals representing a plurality of predetermined excursions;

mask circuit means responsive to said first and second sets of signals and stored mask signals of said mask register for logically generating said first and second subsets of signals; and

comparator circuit means responsive to said last mentioned signals for generating said report signals upon said subsets of signals not being equal.

14. The invention of claim 13 wherein said packet switching system further comprises processor means and means interconnecting said processor means to said switching network;

said processor means supplying said set of mask signals to said interface means via said network and said interconnecting means; and

said interface means further comprising means responsive to supplied set of mask signals to store the latter in said mask register.

15. The interface means in accordance with claim 11 wherein said calculating means comprises accumulator means responsive to each of said error signals for incrementing by one;

and

a present error register responsive to said control signal to store the most significant signals of said accumulator means for generating said first set of signals.

16. The interface means in accordance with claim 15 wherein said accumulator means further comprises means responsive to said control signal for effecting a predetermined division of the contents of said accumulator means.

17. The interface means in accordance with claim 11 wherein said means for generating said control signal comprises:

means responsive to said valid packet signals and said error signals for generating packet present signals;

a counter circuit decremented in response to each of said packet present signals for counting said predetermined number of packets;

means responsive to said counter circuit decrementing to zero for generating said control signal indicating the receipt of said predetermined number of packets;

constant register means for storing signals representing said predetermined number of packets; and

means responsive to said control signal for transferring the contents of said constant register means to said counter circuit to initialize said counter circuit for calculation of said predetermined number of packets.

18. The invention of claim 17 wherein said packet switching system further comprises processor means and means interconnecting said processor means to said switching network;

said processor means supplying said signals representing said predetermined number of packets to said interface means via said network and said interconnecting means; and

said interface means further comprising means responsive to supplied signals representing said predetermined number of packets to store the latter in said constant register means.

19. An error monitoring arrangement for measuring the rate of errors occurring in the transmission of packets, and comprises:

means responsive to incorrect ones of a predetermined number of packets for calculating present error signals representing an error rate;

means for storing reference error signals;

means for deriving a control signal upon receipt of said predetermined number of packets;

means cooperating with said calculating means and said storing means for defining error rate thresholds; and

means cooperating with said defining means, said calculating means, and said storing means in response to said control signal for indicating error rate excursions beyond said thresholds by said present error signals from said reference error signals.

20. The error monitoring arrangement in accordance with claim 19 wherein said means for deriving said control signal comprises:

means responsive to each of said incorrect and correct ones of said packets for generating packet present signals;

a counter circuit decremented in response to each of said packet present signals for counting said predetermined number of packets;

means responsive to said counter circuit decrementing to zero for generating said control signal indicating the receipt of said predetermined number of packets;

constant register means for storing signals representing said predetermined number of packets; and

means responsive to said control signal for transferring the contents of said constant register means to said counter circuit to initialize said counter circuit for calculation of said predetermined number of packets.

21. The error monitoring arrangement in accordance with claim 19 wherein said calculating means comprises accumulator means responsive to said incorrect ones of said packets for generating said present error signals;

and

means for operating said accumulator means upon said predetermined number of packets being received for effecting a predetermined division of said present error signals.

22. The error monitoring arrangement in accordance with claim 19 wherein said defining means comprises:

mask register means for storing a plurality of mask signals;

mask circuit means responsive to said present error signals, reference error signals, and stored mask signals for logically generating a first and a second sets of mask output signals; and

said indicating means comprising means for comparing said sets of mask output signals to indicate said error rate excursions upon said sets of mask output signals not being equal.

23. An error monitoring arrangement for measuring the rate of errors occurring in the transmission of packets, and comprises:

means for generating error signals upon receipt of incorrect ones of said packets;

means for generating valid packet signals upon receipt of correct ones of said packets;

means responsive to said valid packet signals and said error signals for generating a control signal upon a receipt of a predetermined number of packets;

accumulator means incremented in response to each of said error signals for calculating signals representing the number of packets received in error during said predetermined number of packets;

a present error register responsive to said control signal for storing signals of said accumulator means as a first set of signals;

a previous error register for storing a second set of signals representing a previous error rate for a previous predetermined number of packets;

register means for storing a set of mask signals representing a plurality of predetermined thresholds;

circuit means responsive to said first and second sets of signals and stored mask signals for logically generating a first and second subsets of signals; and

comparator means responsive to said subsets of signals for generating a report signal to indicate error rate excursions beyond said thresholds; and

said previous error register comprising means responsive to said control signal and a predetermined one of rate signals for storing the contents of said present time register as said second set of signals.

24. A method of error rate monitoring in a packet switching system for communicating a plurality of packets having a packet switching network, transmission means, and an interface facility interconnecting said transmission means and said switching network, and comprises the steps:

detecting receipt of incorrect ones of said packets by said interface facility;

detecting receipt of correct ones of said packets by said interface facility;

calculating a predetermined number of packets in response to said detection of correct and incorrect packets by said interface facility;

calculating a first set of signals representing the error rate occurring in said predetermined number of packets in response to said detection of said incorrect ones of said packets by said interface facility;

storing a second set of signals representing a reference error rate by said interface facility;

selecting a first and second subsets of signals from said first and second sets of signals by said interface facility, respectively;

comparing said first and second subsets of selected signals by said interface facility; and

generating a report signal indicating excursions of said calculated error rate beyond said reference error rate by said interface facility upon said first and second subsets of selected signals not being equal.

25. The invention of claim 24 wherein said selecting step further comprises the step of masking said first and second sets of signals with a set of mask signals for generating said first and second subsets of signals, respectively, by said interface facility.

26. The invention of claim 24 wherein said step of calculating said predetermined number of packets comprises the steps:

storing a set of signals representing said predetermined number of packets by said interface facility; and

decrementing the stored set of signals to zero in response to the detection of said incorrect and correct ones of said packets to determine said predetermined numbar of packets by said interface facility.

27. The invention of claim 26 wherein said packet switching system further comprises processor means and said storing step further comprises the step of said processor supplying said set of signals representing said predetermined number of packets to said interface facility.

28. The invention of claim 24 wherein said step of calculating said error rate further comprises the step of performing a predetermined division of said first set of signals in preparation for the next predetermined number of packets.