Matrix character reading system

• US 4,490,853 A
• Filed: 12/17/1981
• Issued: 12/25/1984
• Est. Priority Date: 12/17/1981
• Status: Expired due to Term

• Current Assignee: NCR Canada Limited (NCR Corporation)
• Original Assignee: NCR Corporation
• Inventors: Nally, Robert B., Akister, James F., Leung, Patrick C., Vance, Eric J.
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/331,946
• Time in Patent Office: 1,104 Days
• Field of Search: 382/7, 382/9, 382/48, 382/64
• US Class Current: 382/291
• CPC Class Codes: G06V 10/10 Image acquisition document image scanning and transmission H04N1/00; control of digital cameras H04N23/60
• CPC Class Codes: G06V 10/20 Image preprocessing
• CPC Class Codes: G06V 10/24 Aligning, centring, orientation detection or correction of the image
• CPC Class Codes: G06V 10/28 Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns
• CPC Class Codes: G06V 30/2253 Recognition of characters printed with magnetic ink G06V30/2247 takes precedence

Abstract

A method and apparatus for selecting the start of an unknown character sensed by a character recognition system. A multi-channel read head develops a plurality of analog waveforms which form the image of an unknown character sensed by the read head. After the analog waveforms have been digitized and rectified, static and dynamic threshold values are applied producing a multi-column binary bit map of the unknown character. The start of the character is detected when two adjacent rows of the bit map are found to have five consecutive binary bits representing a character. The end of the character is detected when the rows of the binary bits representing background data have a width which is inversely proportional to the width of the character detected. This information is used by a character recognition apparatus in locating the start of the character and the data generated during a character recognition operation.

Claims

1. A method for establishing the location of an unknown character in a character recognition system comprising the steps:

(1) generating a plurality of substantially parallel analog waveforms having varying peak voltage amplitudes and times of occurrence of same representing the configuration of the unknown character;

(2) generating a plurality of first digital values representing the voltage amplitudes in each of the analog waveforms;

(3) applying a first threshold value to said first digital values for generating a plurality of second digital values representing the unknown character and the background of the character;

(4) detecting the start of the unknown character from the second digital values;

(5) generating a second threshold value from said first digital values;

(6) applying said second threshold value to said first digital values for generating third digital values representing the unknown character and fourth digital values representing the background area of the unknown character;

(7) detecting the start of the unknown character from the third and fourth digital values;

(8) and detecting the end of the unknown character from the third and fourth digital values.

2. The method of claim 1 in which the step of generating a second threshold value comprises the steps of detecting the first digital value having the maximum values and dividing the maximum value by a constant.

3. The method of claim 1 in which the step of detecting the end of the character comprises the steps of:

counting the number of third digital values representing the width of the unknown character;

generating the number of fourth digital values representing the background of the character which must follow the end of the character;

counting the number of fourth digital values which follow the end of the character;

and outputting a signal indicating the end of the character upon the number of fourth digital values required to follow the character being equal to the number counted.

4. A method for establishing the start of a symbol represented by a plurality of analog waveforms having peak voltage amplitudes and times of occurrence of same comprising the steps of:

sampling portions of each analog waveform to generate first binary values representing the voltage amplitude of each portion;

comparing each of the first binary values with a first threshold value to provide second binary values representing the voltage amplitude of each portion which exceeds the threshold value;

examining the second binary values for the start of the symbol;

examining the first binary values to find the maximum binary value upon finding the start of a symbol;

dividing the maximum binary value by a constant to produce a second threshold value;

comparing the first binary values with the second threshold value to produce third binary values representing the symbol and fourth binary values representing the background of the symbol;

and examining the third and fourth binary values for the location of the start of the symbol.

5. The method of claim 4 which further includes the steps of:

counting the number of third binary values which comprise the width of the symbol;

counting the number of fourth binary values which follow the end of the symbol;

generating the number of fourth binary values required to follow the end of the symbol in accordance with the number of third binary values counted;

comparing the number of fourth binary values required to follow the symbol with the number counted;

and outputting a signal enabling the symbol to be recognized in response to finding a coincidence between the number of fourth binary values.

6. A method for processing data derived from a plurality of analog waveforms having a sequence of varying peak voltage amplitudes and time of occurrence of same corresponding to the configuration of a character being recognized comprising the steps of:

sampling portions of each analog waveform to generate a plurality of rows of first binary data bits whose value represents the voltage amplitude of each portion;

comparing the value represented by said first binary bits with a first threshold value to produce second binary data bits representing the voltage amplitude of each portion compared which exceeds the first threshold value and third binary data bits which do not exceed the first threshold value;

examining the number and location of each of said second and third binary data bits in each row;

outputting a first signal indicating the start of the character upon finding that there are five consecutive second binary data bits out of the first seven data bits in any row or that the first or seventh binary data bit of the row is a second binary data bit;

examining the values of the second and third binary data bits in each row to find the maximum value in response to the outputting of said first signal;

dividing the maximum value by a constant to output a second threshold value;

comparing the value represented by the second and third binary data bits with said second threshold value to produce fourth binary data bits representing a character and fifth binary data bits representing the background of the character;

examining the number and location of each of said fourth binary data bits;

and outputting a second signal representing the finding of the start of the character upon sensing that five of the first seven binary data bits examined are said fourth binary data bits.

7. The mehtod of claim 6 which further includes the steps of:

counting the number of fourth binary data bits comprising the width of the character;

counting the number of fifth binary data bits that follow the end of the character;

generating the number of fifth binary data bits required to follow the end of the character in accordance with the number of fourth binary data bits counted;

comparing the required number of fourth binary data bits with the number of fourth binary data bits counted;

and outputting a third signal enabling the character to be recognized in response to the finding of a coincidence between the required number of fifth binary data bits and the number of fifth binary data bits counted.

8. A system for processing signals representing feature characteristics of an unknown character comprising:

first means for generating a plurality of adjacent parallel rows of first and second feature characteristic signals in which the first feature characteristic signals represents a feature characteristic of an unknown character and said second feature characteristic signals represents the background of the unknown character;

first means for detecting a first predetermined number of consecutive first feature characteristic signals in two adjacent rows representing the start of the unknown character, said detecting means outputting a first control signal in response to detecting said first predetermined number of first feature characteristic signals;

means for counting the number of first feature characteristic signals representing the width of the unknown character;

and second means for detecting a second predetermined number of said second feature characteristic signals located adjacent the end of said first feature characteristic signals, said second predetermined number being inversely proportional to the number of first feature characteristic signals in the width of the unknown character, said second detecting means outputting a second control signal in response to detecting said second predetermined number whereby a utilization device receives said first and second control signals enabling said utilization device to process said first and second feature characteristic signals.

9. The system of claim 8 in which said first generating means includes:

a multi-channel sensing member for generating a plurality of concurrent voltage signals each having an analog waveform unique to the unknown character, said waveforms including a sequence of varying peak amplitudes;

means connected to said sensing member for converting each of said analog waveforms into a plurality of first digital signals having a signal level corresponding to the peak amplitudes of the analog waveform;

means for comparing the signal level of said first digital signals with a first reference signal level to output a first data signal when the signal level of said first digital signals exceeds said first reference signal level and a second data signal when the signal level of said first digital signals does not exceed the reference signal level;

means for examining said first and second data signals to output a third control signal upon finding a predetermined number of consecutive first data signals;

and means connected to said comparing means and enabled by said third control signal for generating a second reference signal level in accordance with the signal level of said first data signals whereby said comparing means compares the signal level of said first data signals with said second reference signal level to output said first feature characteristic signals when the signals level of one of said first data signals exceeds said second reference signal level and said second feature characteristic signal when it does not exceed the second reference signal level.

10. The system of claim 9 in which said generating means includes third detecting means for detecting the maximum signal level of said first digital signals and first memory means connected to said comparing means and said third detecting means includes means for dividing the maximum signal level detected by a constant to output a second reference signal level to said comparing means.

11. The system of claim 10 in which said examining means includes second memory means connected to said comparing means and adapted to output a fourth control signal upon finding a predetermined number of consecutive first data signals outputted by said comparing means and first logic circuit means connected to said second memory means for outputting said third control signal in response to receiving said fourth control signal.

12. The system of claim 11 in which said first and second memory means each comprises a ROM memory device.

13. The system of claim 12 in which said first detecting means includes first counter means for counting the number of said first and second feature characteristic signals and second logic circuit means connected to said counter means and said second memory means for outputting said first control signal upon the generation of said fourth control signal.

14. The system of claim 13 in which said first counter means is adapted to output a fifth control signal to said second logic circuit means upon reaching a predetermined count whereby said second logic circuit means will output said first control signal upon receiving said fifth control signal.

15. The system of claim 14 in which said second detecting means includes third generating means for generating a first binary signal representing the width of the character sensed, third memory means connected to said third generating means for outputting second binary signals representing the width of the background area which is required to follow the width of the character sensed and fourth means for generating a sixth control signal indicating the end of the character upon the value of the second binary signal equalling the value of the first binary signal.

16. The system of claim 15 in which said third generating means includes second counter means connected to said second logic circuit means for counting the number of consecutive first feature characteristic signals in response to the generation of said first control signal, fourth detecting means for detecting the transition between the generation of said first and second feature characteristic signals and means for outputting the count of said second counter means as the width of the character sensed in response to the detection of the end of the character by said fourth detecting means.

17. The system of claim 16 in which said second detecting means further includes third counter means connected to said third memory means, said third counter means being preset to a value represented by said second binary signals and operated to downcount said second feature characteristic signals to output a seventh control signal upon reaching the value of zero and third logic circuit means connected to said third counter means to output an eighth control signal in response to receiving said seventh control signal indicating the position of the end of the character in said feature characteristic signals.