Self-substrate-bias circuit device

• US 4,491,746 A
• Filed: 09/21/1981
• Issued: 01/01/1985
• Est. Priority Date: 09/24/1980
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Koike, Hideharu
• Primary Examiner(s): Anagnos, Larry N.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US06/304,035
• Time in Patent Office: 1,198 Days
• Field of Search: 307/296 A, 307/304, 307/296 R, 307/303, 357/23 C, 357/42, 357/41, 357/23 CS
• US Class Current: 327/534
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures

Abstract

A self-substrate-bias circuit device comprising substrate of P conductivity type, a capacitor element of MOS construction formed in said semiconductor substrate and whose one end is connected to the output terminal of a pulse generator, a diode element formed in said semiconductor substrate and connected between the other end of said capacitor element and a ground potential, and an P⁺ region of P conductivity type formed in the region of said seminconductor substrate which is contacted to said capacitor element and having higher impurity concentration than that of said semiconductor substrate.

Claims

1. A self-substrate-bias circuit device for use with a pulse generator comprising:

a semiconductor substrate of a given conductivity type;

a capacitor element of MOS construction formed in said semiconductor substrate having a first side connected to the output terminal of the pulse generator;

a first diode formed in said semiconductor substrate and connected between the other side of said capacitor element and a reference potential; and

a region of said conductivity type formed in a portion of said semiconductor substrate which is contacted to and surrounding said capacitor element and having higher impurity concentration than that of said semiconductor substrate so that carriers from said capacitor element recombine with carriers existing in said region.

2. A self-substrate-bias circuit device according to claim 1 further including a second diode formed between the other side of said capacitor element and said semiconductor substrate.

3. A self-substrate-bias circuit device according to claim 1 or 2 wherein said capacitor element is of N-channel type.

4. A self-substrate-bias circuit device according to claim 1 or 2 wherein said capacitor element is of P-channel type.

5. A self-substrate-bias circuit device according to claim 1 or 2 wherein said first and second diodes are MOS-constructed.

6. A self-substrate-bias circuit device according to claim 5 wherein said first and second diodes are of N-channel type.

7. A self-substrate-bias circuit device according to claim 5 wherein said first and second diodes are of P-channel type.

8. A self-substrate-bias circuit device according to claim 1 wherein said reference potential is a ground potential.

9. A self-substrate-bias circuit device according to claim 2 wherein said region is formed to surround said capacitor element and said two diodes.

10. A self-substrate-bias circuit device according to claim 2 wherein each of said diodes has an anode and a cathode section separated by a region which is of said given conductivity type and has an impurity concentration lower than that of said region contacted to and surrounding said capacitor element.