Fast packet switch

• US 4,491,945 A
• Filed: 06/25/1982
• Issued: 01/01/1985
• Est. Priority Date: 06/25/1982
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: AT&T, Inc.
• Inventors: Turner, Jonathan S.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/392,378
• Time in Patent Office: 921 Days
• Field of Search: 370/60, 370/94, 370/92, 370/93, 370/58
• US Class Current: 370/409
• CPC Class Codes: H04L 49/10 characterised by the switching fabric construction
• CPC Class Codes: H04L 49/118 Address processing within a device, e.g. using internal ID or tags for routing within a switch
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports

Abstract

A communication method and packet switching system in which packets comprising logical addresses and voice/data information are communicated through the system by packet switching networks which are interconnected by high-speed digital trunks with each of the latter being directly terminated on both ends by trunk controllers. During initial call setup of a particular call, central processors associated with each network in the desired route store the necessary logical to physical address information in the controllers which perform all logical to physical address translations on packets of the call. Each network comprises stages of switching nodes which are responsive to the physical address associated with a packet by a controller to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols. Each packet has a field which is automatically updated by the controllers for accumulating the total time delay incurred by the packet in progressing through the networks. Each processor has the capability of doing fault detection and isolation on the associated network, trunks, and controllers by the transmission of a single test packet. The testing is done solely in response to the test packet and no preconditioning of controllers or networks is necessary.

Claims

1. A packet switch comprising

a plurality of input conductors,

a plurality of output conductors,

means responsive to a predetermined group of a plurality of address bits in a packet of information bits from one of said input conductors for routing said packet of information bits to one of said output conductors defined by said predetermined number of address bits, and

means for repositioning said predetermined number of address bits in said plurality of address bits in the routing of said packet to said defined one of said output conductors.

2. The invention of claim 1 wherein

said predetermined number of said address bits comprise the most significant address bits in said packet and

said repositioning means relocates said most significant bits to a less significant bit position in said plurality of address bits.

3. The invention of claim 2 wherein said repositioning means comprises:

first and second shift register circuits each having an input and an output means,

said input means of said first shift register circuit connected to said routing means for receiving said packet of information bits therefrom and said input means of said second shift register circuit connected to said output means of said first shift register circuit for receiving said packet of information bits therefrom,

selecting means operable for selecting information bits from said output means of said first and second shift register circuits, and

control circuit means responsive to said plurality of address bits for operating said selecting means sequentially to select said information bits from said first and second shift register circuits to effect a rotation of said most significant address bits to said least significant bit position in said plurality of address bits.

4. A fast packet switching network comprising

a plurality of input conductors,

a plurality of output conductors,

a plurality of switching nodes interposed between said plurality of input and output conductors, each of said nodes comprising

means responsive to a receipt of predetermined number of address bits in a packet of information received from one input conductors for routing said packet to a subsequent one of said nodes or to said output conductors, and

means for repositioning said predetermined number of address bits to a different location is said packet incident to said routings.

5. The invention of claim 4 wherein

said predetermined number of address bits comprise the most significant address bits in said packet, and

said repositioning means relocates said most significant bits to a less significant bit position in said packet.

6. The invention of claim 5 wherein said repositioning means comprises:

first and second shift register circuits each having an input and an output means said input means of said first shift register circuit connected to said routing means for receiving said packet of information therefrom, and said input means of said second shift register circuit connected to said output means of said first shift regiser circuit for receiving said packet of information,

selecting means operable for selecting said packet of information from said output means of said first and second shift register circuits, and

control means responsive to said address bits for operating said selecting means to sequentially select said packet of information to effect a rotation of said most significant bits to said least significant bit positions in said packet of information.

7. A packet switch for switching packets of digital signals between a plurality of input terminals and plurality of output terminals, and said switch comprising:

a plurality of input control means each of which is connected to an individual one of said input terminals,

a plurality of output control means each of which is connected to an individual one of said output terminals,

means individually connecting each of said input control means to each of said output control means,

each of said packets comprising an address field of said digital bit signals defining a packet communication path from an individual one of said input control means over said connecting means and an individual one of said output control means to said individual one of said output terminals connected thereto,

means for storing address and other digital bit signals of a packet received from said individual one of said input terminals,

means for controlling said storing means to commence a transmission therefrom of address and other digital bit signals of said received packet to the one of said output terminals identified by the stored address signals of said packet immediately upon receipt of a control signal indicating an idle condition of said defined one of said output terminals

means responsive to a predetermined number of a plurality of address bits in said received packet for routing said stored address and other digital bit signals to said defined one of said output terminals, and

means for repositioning said predetermined number of address bits in said plurality of address bits in the routing of said packet to said defined one of said output terminals.

8. The invention of claim 7 wherein

said predetermined number of address bits located in a most significant address bit position in said packet, and said repositioning means relocates said predetermined number of address bits to a least significant address bit position in said packet.

9. A packet switch for switching packets of digital signals between a plurality of input terminals and a plurality of output terminals, and said switch comprising:

a plurality of input control means each of which is connected to an individual one of said input terminals,

a plurality of output control means each of which is connected to an individual one ot said output terminals, means individually connecting each of said input control means to each of said output control means,

each of said packets comprising an address field of said digital bit signals defining a packet communication path from an individual one of said input control means over said connecting means and an individual one of said output control means to said individual one of said output terminals connected thereto,

means responsive to a predetermined number of address bits in said address field of a packet of digital signals received from said individual one of said input terminals for routing said received packet to the one of said output terminals defined by said predetermined number of address bits, and

means for repositioning said predetermined number of address bits in said address field in the routing of said received packet to said defined one of said output terminals.

10. The invention of claim 9, further comprising

means for storing said digital bit signals of said packet received from said individual one of said input terminals, and

means for controlling said storing means to commence a transmission therefrom of said stored digital bit signals.

11. A packet switch for switching packets of digital signals between a plurality of input terminals and a plurality of output terminals, and said switch comprising:

a plurality of input control means each of which is connected to an individual one of said input terminals,

a plurality of output control means each of which is connected to an individual one of said output terminals,

means individually connecting each of said input control means to each of said output control means,

each of said packets comprising an address field of said digital bit signals defining a packet communication path from an individual one of said input control means over said connecting means and an individual one of said output control means to said individual one of said output terminals connected thereto, and

means for repositioning said digital bit signals of said address field of each packet received from said individual one of said input terminals in a routing of said received packet over defined packet communication path.

12. The invention of claim 11, wherein

said defined communication path is specified by a predetermined number of digital bit signals of said address field in said received packet, and

said repositioning means comprises means in said individual one of said input control means for rearranging said predetermined number of said digital bit signals of said address field in a routing of said digital bit signals in said address field over the specified communication path.

13. The invention of claim 12 wherein each of said input control means further comprising

means for storing said digital bit signals of said received packet from said connected individual one of said input terminals, and

means for controlling said storing means to commence a transmission therefrom of said stored digital bit signals.

14. The invention of claim 12 wherein said rearranging means of said repositioning means comprises:

first and second shift register circuits each having an input and an output means said input means of said first shift register circuit connected to said storing means for receiving said stored digital bit signals therefrom, and said input means of said second shift register circuit connected to said output means of said first shift register circuit for receiving said stored digital bit signals therefrom,

selecting means operable for selecting said digital bit signals of said address field from said output means of said first and second shift register circuits, and

control circuit means responsive to said digital bit signals of said address field for operating said selecting means sequentially to select said digital bit signals of said address field from said first and second shift register circuits to effect a rotation of said predetermined number of said digital bit signals of said address field to a least significant bit position of said address field.

15. A packet switch for switching packets of digital signals between a plurality of input terminals and a plurality of output terminals, and said switch comprising:

a plurality of input control means each of which is connected to an individual one of said input terminals,

a plurality of output control means each of which is connected to an individual one of said output terminals,

means individually connecting each of said input control means to each of said output control means,

each of said packets comprising an address field of said digital signals defining a packet communication path from an individual one of said input control means over said connecting means and an individual one of said output control means to said individual one of said output terminals connected thereto,

the defined one of said input control means comprising controller means responsive to a receipt of said address field signals for sending a packet communication request signal over said connecting means to said individual one of said output control means,

the defined one of said output control means comprising control circuitry for supplying a signal over said connecting means to each of said input control means to signify the packet communication availabilty of said output control means and said individual one of said output terminals connected thereto, and

means in said each input and output control means responsive to tne supplied availability and request signals for communicating digital signals of a received packet over the defined packet communication path from said defined one of said input control means over said connecting means and defined one of said output control means to the defined one of said output terminals connected thereto.

16. A packet switch according to claim 15 wherein

said input control means further comprises buffer means for storing received packet digital signals and

said controller means is responsive to address field signals stored in said buffer means for sending said packet communication request signal over said connecting means to said defined one of said output control means.

17. A packet switch according to claim 16 wherein

said buffer means comprises a plural stage buffer shift register for storing said packet digital signals and having a first stage, intermediate stages and a last stage, and being operative in response to a sequential receipt of packet digital signals for shifting the received digital signals from said first stage intermediate stages toward said last stage, each of said register stages comprising stage output means for deriving the shifted digital signals thereat,

selector means operable for selecting a one of said stage output means storing a start-of-packet digital signal of said received packet and to commence a communication of said received packet from said selector means toward said defined one of said output control means, and

said controller means being further responsive for operating said selector means upon receipt of said packet communication availability signal.

18. A packet switch according to claim 17 wherein

said buffer means further comprises a plural stage input shift register having an input for sequentially receiving packet digital signals to effect a storage of said digital signals in said input shift requests, a serial output for sequentially supplying the stored packet digital signals to said buffer shift register, and address bit outputs for deriving stored address bit signals of said received digital signals,

further comprising an address register operable for registering said stored address bit signals identifying that said defined one of said output control means is to receive said stored packet digital signals, and

said controller means being further responsive to a start-of-packet signal stored in said input shift register ano to address bit signals stored in said address register for sending said packet communication request signal over said connecting means to said defined one of said output control means.

19. A packet switch according to claim 18 wherein said input shift register further comprises output means furnishing signals signifying the length of the packet stored therein,

further comprising a packet length register means responsive to said packet length signals for activating said controller means to control said selector means for terminating said communication of said packet from said selector means toward said defined one of said output control means.

20. A packet switch according to claim 19 further comprising:

device means operable for supplying said packet communication available signal to said individual one of said input terminals connected to said each input control means, and wherein

said controller means is further activated by said packet length register means to control the operation of said device means upon a terminating of said communication of said packet from said selector means toward said defined one of said output control means.

21. A packet switch according to claim 18 wherein

said address field digital signals comprise most significant and less significant bit signals and

said communicating means further comprises address rotation means controlled by said controller means for rotating said most significant and less significant bit signals of the packet of digital signals communicated from said selector means.

22. A packet switch according to claim 21 wherein said communicating means further comprises:

multiplexer means operative under control of said controller means for communicating the packet of digital signals with rotated address bit signals from said address rotation means to said defined one of said output control means.

23. A packet switch according to claim 21 wherein said address rotation means comprises:

first and second shift register circuits each having an input and output means said input means of said first shift register circuit connected to said selector means for receiving said packet digital signals therefrom, and said input means of said second shift register circuit connected to said output means of said first shift register circuit for receiving packet digital signals therefrom,

selecting means operable for selecting packet digital signals from said output means of said first and second shift register circuits, and

control circuit means operative under control of said controller means for operating said selecting means sequentially to select packet digital signals from said first and second shift register circuits to effect a rotation of said most significant and less significant bit signals of said packet of digital signals communicated from said selector means.

24. A packet switch according to claim 23 wherein said defined one of said output control means further comprises:

logic means connected to said defined one of said output conductors for detecting the availability of said defined one of said output conductors for packet communication, and

said control circuitry being responsive to a detection of said availability by said logic means for sending said packet communication available signal over said connecting means to the defined one of said input control means.

25. A packet switch according to claim 23 wherein

said logic means further is operative under control of said control circuitry in response to a receipt of said packet communication request signal for signaling an engagement of said defined one of said output control means for packet communication.

26. A packet switch according to claim 25 wherein said defined one of said output control means further comprises:

selector circuitry operable for selecting packet digital signals received from said defined one of said input control means over said connecting means for communication to said defined one of said output conductors, and

said control circuitry is activated by said logic means and a received packet communication request signal from said defined one of said input control means for operating said selector circuitry.

27. A packet switching network comprising first and second switching stages each having a plurality of switching elements,

each of said elements comprising a plurality of input and output terminals,

each of said input terminals of said first stage being connectable to an individual input conductor,

means connecting each of said output terminals of said first stage to an individual one of said input terminals of said second stage,

each of said output terminals of said second stage being connectable to an individual output conductor,

each of said elements further comprising for each one of said input terminals thereof:

means for storing address and other digital signals of a packet received on said each one of said input terminals;

controller means for controlling said storing means to commence a transmission therefrom of said address and other digital signals of said packet upon a receipt of a control signal indicating an idle condition of the one of said output terminals identified by the stored address signals of said packet in said storing means;

means responsive to a storage of a ready signal in said storing means for supplying an idle condition indicating signal to said each one of said input terminals;

said supplying means comprises logic means operable for supplying said idle condition indicating signal to said each one of said input terminals and

further comprising for each one of said input terminals length register means for registering the length of a received packet in response to packet length digital signals storage in said storing means, and

said controller means being controlled by said registered packet length signals in said registering means for operating said logic means.

28. The invention of claim 27 wherein

said storing means further comprises

an input shift register for sequentially storing start-of-packet, address and other digital signals of a packet received on said each one of said input terminals;

and

a buffer shift register for buffer storing received signals of said packet from storage of said input shift register.

29. The invention of claim 27 wherein

each of said elements further comprises for said each one of said output terminals thereof,

output control means comprising means for supplying said control signal to indicate that said one of said output terminals thereof is in an idle condition, and

said controller means for said one of said input terminals is responsive to said stored address signals in said storing means for sending a packet communication request signal to one of said output control means identified by said stored address signals.

30. The invention of claim 29 wherein each of said switching elements further comprises for said each one of said input terminals thereof

means operable for extracting stored digital signals of said packet from said storing means for commencing transmission of said stored digital signals therefrom to said one of said output control means identified by said stored address signals, and

said controller means for said one of said input terminals is responsive to a receipt of the supplied control signals from said identified output control means for operating said extracting means to commence said transmission of digital signals from said storing means.

31. The invention of claim 27 wherein said address digital signals of said packet comprises most significant and lesser significant bits,

said most significant bits identifying an individual one of said output control means, and

each of said switching elements further comprises rotating means for rearranging said significant and said lesser significant bits for said each one of said input terminals thereof

32. The invention of claim 31 wherein said rotating means comprises:

a series arrangement of first and second shift registers for receiving said digital signals of said packet from said extracting means, each of said first and second registers comprising an individual output,

selector circuitry operable for sequentially selecting said each of said individual output for order rotating said most significant and lesser significant bits, and

control circuitry activated during a transmission of said digital signals of said packet for effecting sequential operations of said selector cirrcuitry.

33. The invention of claim 32 wherein

each of said switching elements further comprises for said each one of said input terminals thereof

means multiplexing digital signals of said packet received from said selector circuitry thereof for transmission to said individual one of said output control means identified by said rotated most significant bits.

34. The invention of claim 27 wherein

each of said switching elements further comprises for said each one of said output terminals thereof,

output control means comprising

control circuitry operable for supplying said control signal, and

logic means responsive to an idle condition indicating signal on said each one of said output terminals thereof for effecting an operation of said control circuitry.

35. The invention of claim 34 wherein

said controller means for said each one of said input terminals is responsive to said stored address signals in said storing means for sending a packet communication request signal, and

said output control means further comprises selector circuitry operable for selecting received digital signals of said packet for transmission to said each one of said output terminals identified by said stored address signals of said packet in said storing means, and

said control circuitry is responsive to a receipt of said request signal for effecting an operation of said selector circuitry.

36. A packet switch for switching packets of digital signals from an input conductor to a plurality of output conductors and said switch comprising:

an input control means connected to said input conductor,

a plurality of output control means each of which is connected to an individual one of said output conductors,

means individually connecting said input control means to each of said output control means,

said input control means comprising controller means responsive to a receipt of address digital signals of a packet over said input conductor for sending a packet communication request signal over said connecting means to an individual one of said output control means defined by said address digital signals, and

said defined output control means comprising control circuitry responsive to said request signal and to a control signal on said output conductor connected to said defined output control means for sending a packet communication available signal over said connecting means to said input control means.

37. A packet switch according to claim 36 wherein said input control means further comprises:

buffer means for sequentially storing packet start, address, and data signals of said packet received on said input conductor and

means for sequentially extracting the stored packet start, address, and data digital signals from said buffer means upon a receipt of said packet communication available signal.

38. A packet switch according to claim 37 wherein

said buffer means comprises plural output means for supplying said stored digital signals,

said extracting means comprises selector means operable for selecting one of said plural output means for supplying said stored packet start signal upon a receipt of said packet communication available signal, and

said controller means being responsive to a receipt of said packet communication available signal for operating said selecting means to specify said one of said plural output means supplying said stored packet start signal.

39. A packet switch according to claim 38 wherein said buffer means comprises a serially connected pair of shift register means.

40. A packet switch according to claim 39 wherein a first one of said pair of shift register means comprises an input communicating with said input conductor, a plurality of bit outputs defining a packet start bit output, packet length bit outputs, and address bit outputs, and a register output for serially communicating stored packet start, address and data digital signals to said second one of said pair of shift registers.

41. A packet switch according to claim 40 further comprising:

address register means responsive to address signals on said address bit outputs of said first shift register means for activating said controller means for sending said packet communication request signal over said connecting means to said output control means defined by said address digital signals.

42. A packet switch according to claim 40 wherein said second one of said pair of shift registers comprises said plural output means and is operative in response to digital signals from said register output for sequentially shifting said packet start, address and data digital signals successively to each of said plural output means.

43. A packet switch according to claim 42 further comprising:

multiplexer means controlled by said controller means for communicating received digital signals over said connecting means to said defined output control means,

address rotation means cooperating with said controller means and said selector means for rotating said address digital signals in communicating said packet start, address and data digital signals to said multiplexer means.

44. A packet switch according to claim 40 further comprising:

packet length register means for storing packet length signals received from said packet length bit outputs of said first one of said shift register means and

device means operable for supplying said control signal to said input conductor, and wherein

said controller means is activated by the packet length signal storage in said packet length register to control the operation of said device means upon a transmission of said packet from said second one of said pair of shift registers.

45. A packet switch according to claim 43 wherein

said defined output control means further comprises:

logic means responsive to said control signal for signaling said control circuitry of the packet communication availability of said output conductor connected to said defined output control means, and

said control circuitry being responsive to said signaling for sending said packet available signal over said connecting means to said input control means.

46. A packet switch according to claim 45 wherein

said logic means further is operative under control of said control circuitry for signaling an engagement of said defined output control means for packet communication over said output conductor connected thereto.

47. A packet switch according to claim 45 wherein said defined output control means further comprises:

selector circuitry operable for selecting packet digital signals received over said connecting means from said input control means for communication to said output conductor connected to said defined output control means, and

said control circuitry is further responsive to said packet communication availability signaling for operating said selector circuitry.

48. A packet switch according to claim 47 wherein said defined output control means further comprises

a logic device cooperating with said control circuitry and said selector circuitry for communicating selected packet digital signals received from said input control means over said connecting means to said output conductor connected to said defined output control means.

49. A method of switching packets through a packet switching network comprising a first and a second stage with each stage being comprised of switching elements, each switching element having a plurality of input and output terminals, each of said switching elements of said first stage has an individual one of said output terminals connected to each of said switching elements of said second stage via the input terminals of said switching elements of said second stage, each switching element of said first and second stages having a storage means for variably buffering packets, said switching elements are responsive to an address contained within packets to route the packets from the input terminals to the address designated output terminals, and comprises the steps of

storing the first portion of a packet received on the input terminal of one of said switching elements of said first stage;

decoding said address field of said packet; and

transmitting said portion of said packet to the connected input terminal of a switching element of said second stage via the output terminal of said one of said switching elements of said first stage designated by said address field of said packet.

50. The invention of claim 49 further comprising the step of transmitting a link open signal upon the storage means associated with said connected input terminal of said switching element of said second stage being capable of receiving said packet from said switching element of said first stage.

51. The invention of claim 50 wherein said transmitting of said portion of said packet step further comprising the step of responding to said link open signal by said switching element of said first stage to transmit said portion of said packet to said switching element of said second stage.

52. The invention of claim 51 wherein said step of transmitting said packet from said first stage to said second stage further comprises the step of performing said transmission bit serially.

53. The invention of claim 49 wherein the step of transmitting said portion of said packet includes the step of rotating the most significant bits of said address field so that said most significant bits become the least significant bits.

54. The invention of claim 53 wherein said step of rotating said address field further comprising the steps of storing said most significant bits;

transmitting the remaining portion of said address field;

transmitting said most significant bits upon transmission of said remaining portion of said address field.

55. A method of switching packets of digital signals between a plurality of input terminals and a plurality of output terminals via a switch comprising a plurality of input control means each of which is connected to an individual one of said input terminals, a plurality of output control means each of which is connected to an individual one of said output terminals, means individually connecting each of said input control means to each of said output control means, and each of said packets comprising an address field defining the communication path from an individual one of said input control means over said connecting means and individual one of said output control means to said individual one of said output terminals connected thereto and another plurality of input terminals, another plurality of output terminals, another plurality of input control means and another plurality of output control means, each output terminal of said stage connected to an individual one of said input terminals of said other stage, and each of said input control means of said stage and said other stage having an associated buffer for variably storing said packets, and comprises the steps:

transmitting a request signal over said individual connecting means to said designated individual one of said output control means in response to the receipt of said address field;

transmitting a grant signal to said receiving one of said input control means by said designated output control means in response to said request signal to signify the packet communication availability of said output control means and said individual one of said output terminals connected thereto;

transmitting the received packet to said output control means by said input control means in response to said grant signal;

transmitting a link open signal to said connected output terminal of said stage by one of said input terminals of said other stage upon said associated buffer of said one of said input control means of said other stage being capable of receiving a portion of a packet; and

transmitting said grant signal to said connected input control means by said connected output control means of said stage upon receipt of said link open signal from said input control means of said other stage and said request signal from said connected input control means of said stage.

56. The invention of claim 55 wherein said connected output means of said stage further comprising a storage means for storing said link open signal and further comprises the step of setting said storage means to a first state upon receipt of said link open signal;

and

transmitting said grant signal to said connected input control means of said stage upon receipt of said request signal and said storage means containing said first state.

57. A packet switch for switching packets of digital signals between a plurality of input terminals and a plurality of output terminals and comprising:

a buffer means responsive to a receipt of packet digital signals on one of said input conductors for storing said received signals;

means responsive to a receipt of a packet communication available signal for one of said output conductors and to packet address digital signals on said one of said input conductors for commencing a routing of then and subsequently stored digital signals of said received packet to said one of said output conductors; and

means for repositioning a predetermined number of said plurality of address digital signals in the routing of said stored digital signals of said received packet to said one of said output conductors.