RAM Utilizing offset contact regions for increased storage capacitance

• US 4,493,056 A
• Filed: 06/30/1982
• Issued: 01/08/1985
• Est. Priority Date: 06/30/1982
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mao, Robert S.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Gossage, Glenn
• Application Number:
  US06/394,055
• Time in Patent Office: 923 Days
• Field of Search: 365/149, 365/205, 365/208, 365/210, 357/41, 357/45
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

An integrated circuit electronic memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the transfer of binary information through the channel region into and out of the capacitive storage region. Each memory cell also includes an offset contact region which contacts an adjacent bit line. The word lines are arranged in rows and the bit lines are arranged in columns, complementary pairs of bit lines being electrically connected to alternate ones of memory cells along each column. A bit line to diffusion capacitance couples each memory cell to the one of the pair of bit lines to which it is electrically not connected. This capacitance boosts the electrical signal written into and read out from the storage capacitor. Also disclosed is a memory array in which a single sense amplifier and dummy cell arrangement placed near the middle of each column of cells selectively accesses either half of the column.

Claims

1. A memory cell comprising:

a transfer device having a control electrode and an offset contact region, the control electrode being electrically connected to a word line, the contact region being electrically connected to a first bit line;

a storage capacitance operatively connectable to said first bit line by selective actuation of the control electrode of said transfer device; and

a second bit line spaced apart from said first bit line and capacitively coupled to said storage capacitance, wherein said second bit line substantially overlies said storage capacitance and said control electrode, and said first bit line substantially overlies said contact region.

2. A memory cell as in claim 1 wherein said transfer device is a field effect transistor having a drain region, a source region, and a gate electrode underlying said second bit line, the contact region being electrically integral with an extension of the drain region, the control electrode being the gate electrode of the field effect transistor.

3. A memory cell as in claim 2 wherein said storage capacitance comprises:

a conductive plate region connected to a fixed potential, wherein said conductive plate region is arranged substantially orthogonal to said first and second bit lines and is separated from said first and second bit lines and from said semiconductor surface by a dielectric; and

a doped region formed in said semiconductor surface bordering the region therein underlying the crossover area of said second bit line and said conductive plate region, wherein said doped region is electrically integral with said storage capacitance and is capacitively coupled to said second bit line.

4. A memory cell as in claim 3 wherein said doped region is the source region of said field effect transistor.

5. An integrated circuit electronic memory array having a plurality of memory cells arranged in an orthogonal array of rows and columns, each memory cell of said array having a storage region and a transfer device, each transfer device having an offset contact region and a gate region, said array comprising:

a plurality of word lines arranged in rows, each of said word lines being electrically integral with the gate region of each transfer device along a row of memory cells;

a plurality of bit line pairs arranged in columns substantially orthogonal to said word lines, each of said bit line pairs being arranged along each column of memory cells, wherein each bit line in a bit line pair overlies and electrically contacts the offset contact regions of alternate ones of said memory cells in a column, and wherein the opposite bit line in said bit line pair overlies the corresponding storage region and transfer device region of each one of said alternate ones of said memory cells; and

capacitive means coupling each bit line in each of said bit line pairs to said alternate ones of said memory cells thereunder, wherein each memory cell is in electrical contact with one bit line of said bit line pair and is capacitively coupled to and substantially underlies the other bit line of said bit line pair.

6. An integrated circuit memory cell structure comprising:

a semiconductor substrate doped with impurities of a first conductivity type;

a gate oxide formed on portions of said semiconductor substrate;

polysilicon conductors formed on portions of said gate oxide, a first one of said polysilicon conductors forming one plate of a storage capacitance, at least another one of said polysilicon conductors forming a gate electrode of a transfer device;

first and second spaced apart doped regions formed by impurities of opposite conductivity type formed in said substrate in portions thereof substantially not masked by said polysilicon conductors;

an insulator covering said polysilicon conductors and said first and second doped regions;

a first metal bit line on said insulator overlying said first and second doped regions and said polysilicon conductors and forming a capacitance with at least one of said first and second doped regions, thereby capacitively coupling said first metal bit line to said memory cell, said first metal bit line being otherwise electrically isolated from the memory cell with which it is capacitively coupled; and

a third doped region formed by impurities of said opposite conductivity type in said substrate, said third doped region contacting said second doped region and extending laterally from under said first metal bit line to under a second metal bit line, said third doped region being electrically isolated from said first bit line and electrically connected to said second bit line.