Interface circuit for digital signal transmission system

• US 4,493,092 A
• Filed: 12/17/1982
• Issued: 01/08/1985
• Est. Priority Date: 12/17/1982
• Status: Expired due to Fees

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: GTE Automatic Electric Incorporated
• Inventors: Adams, Tello D.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/450,615
• Time in Patent Office: 753 Days
• Field of Search: 375/7, 375/17, 375/36, 307/270, 307/241, 307/443, 179/2 C, 179/2 DP, 370/80, 370/85
• US Class Current: 375/257
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes
• CPC Class Codes: H04L 5/1423 for simultaneous baseband signals

Abstract

A signal transmission system which allows digital signals to be transmitted over twisted pair transmission lines. Master and slave transmission circuits are located at the switching system and terminal ends, respectively, of the transmission line. Both circuits include transmit and receive circuitry. The transmit circuitry includes a summing circuit connected to a constant current generator and the receive circuit includes a differential amplifier connected to a slicer circuit.

Claims

1. An interface circuit for digital signal transmission system for use between first and second digital signaling devices, each device being operative to provide digital device signals of first, second and third characteristics, said digital signal transmission system comprising:

first and second line interface devices connected to said first and second digital signaling devices, respectively;

a transmission line connected between said first and second line interface devices;

each of said first and second line interface devices being operative in response to said digital device signal of said first characteristic to provide bias current in said transmission line; and

each being further operative in response to said digital device signals of said second and third characteristics to modulate said bias current with modulation signals of first and second characteristics, respectively; and

each of said first and second line interface devices being further operative in response to said bias current to provide a digital interface signal of a first characteristic and each being further operative in response to said modulation signals of said first and second characteristics to provide digital interface signals of second and third characteristics, respectively;

said digital signaling devices each being further operative to receive said digital interface signals of said first, second and third characteristics.

2. A digital signaling interface circuit as claimed in claim 1, wherein said first and second line interface devices comprise:

first and second transmitting means, respectively, each connected between said transmission line and said associated digital signaling device, and both operative in response to said digital device signal of said first characteristic to provide said transmission line bias current, and each further operative in response to said digital device signals of said second and third characteristics to provide said modulation signals of said first and second characteristics, respectively.

3. A digital signaling interface circuit as claimed in claim 1, wherein said first and second line interface devices comprise:

first and second receiving means, respectively, each connected between said transmission line and said associated digital signaling device, and each operative in response to said bias current to provide said digital interface signal of said first characteristic, and each further operative in response to said modulation signals of said first and second characteristics to provide said digital interface signals of said second and third characteristics, respectively.

4. A digital signaling interface circuit as claimed in claim 1, wherein said first line interface device comprises a source of power for said transmission line bias current and said modulation signals of first and second characteristics.

5. A digital signaling interface circuit as claimed in claim 1, wherein said second line interface device comprises current directional means being operative to cause said transmission line bias current to be unidirectional within said second line interface device.

6. A digital signaling interface circuit as claimed in claim 2, wherein said first transmitting means comprises a source of power for said transmission line bias current and said first and second modulation signals.

7. A digital signaling interface circuit as claimed in claim 2, wherein said second transmitting means comprises current directional means being operative to cause said transmission line bias current to be unidirectional within said second transmitting means.

8. A digital signaling interface circuit as claimed in claim 7, wherein said current directional means comprises a diode bridge.

9. A digital signaling interface circuit as claimed in claim 2, wherein said digital device signals of said first, second and third characteristics, are each represented by a plurality of different digital data bits, said first and second transmitting means each comprising:

summing means connected to said first and second digital signal devices, respectively, and operative in response to said plurality of data bits representing said digital device signals of said first, second and third characteristics to provide first, second and third current control signals respectively; and

current generating means connected to said summing means and operative in response to said first, second and third current control signals to provide said transmission line bias current and said modulation signals of said first and second characteristics, respectively.

10. A digital signaling interface circuit as claimed in claim 9, wherein there is further included:

filter means connected between said summing means and said current generating means and operative to filter said current control signals of said first, second and third characteristics;

said current generating means being operative in response to said filtered current control signals of said first, second and third characteristics to provide said transmission line bias current and said modulation signals of said first and second characteristics, respectively.

11. A digital signaling interface circuit as claimed in claim 9, wherein said summing means comprises:

first and second resistors connected to a common junction and to said digital signaling device; and

a third resistor connected between said common junction and ground.

12. A digital signaling interface circuit as claimed in claim 9, wherein said current generating means comprises a transistor connected to a resistor.

13. A digital signaling interface circuit as claimed in claim 9, wherein said transmission line includes first and second wires, said current generating means comprising:

a regulatory resistor;

first and second transistors each having base, collector and oppositely poled emitters;

said collectors of said first and second transistors being connected to said first and second wires, respectively, said regulating resistor being connected between said first and second emitters;

a first bias resistor connected across said first base and first collector;

a second bias resistor connected between said first and second bases; and

a third bias resistor connected across said second base and collector;

said second and third bias resistors being further connected to a common junction.

14. A digital signaling interface circuit as claimed in claim 10, wherein there is further included:

a first signal coupling capacitor connected between said filter means and said summing means.

15. A digital signaling interface circuit as claimed in claim 13, wherein there is further included a second signal coupling capacitor connected between ground and said junction between said second and third bias resistors.

16. A digital signaling interface circuit as claimed in claim 13, wherein there is further included, an impedance balancing resistor connected between said second base and said junction between said second and third bias resistors.

17. A digital signaling interface circuit as claimed in claim 3, wherein said receiving means comprises:

a common mode noise rejection receiver connected to said transmission line and operative in response to said transmission line bias current and said modulation signals of said first and second characteristics to provide receiver signals of first, second and third characteristics, respectively; and

signal slicing means having an input lead connected to said common mode noise rejection receiver and a pair of slicer outputs connected to said digital signaling device, said slicing means being operative in response to said receiver signals of first, second and third characteristics to provide said digital interface signals of first, second and third characteristics, respectively.

18. A digital signaling interface circuit as claimed in claim 17, wherein there is further included, an amplifier connected between said common mode noise rejection receiver and said signal slicing means, and operative to amplify said receiver signals.

19. A digital signaling interface circuit as claimed in claim 18, wherein there is further included, a voltage reference source, said amplifier comprising:

an operational amplifier having positive and negative inputs and a receiver output, said negative input being connected to said common mode noise rejection receiver, and said positive input being connected to said voltage reference source; and

a filter connected across said negative input and said receiver output.

20. A digital signaling interface circuit as claimed in claim 17, wherein said transmission line includes first and second wires, said digital signaling system further including, a voltage reference source, said common mode noise rejection receiver comprising:

a differential amplifier having positive and negative inputs and an output;

a first blocking capacitor connected between said negative input and said first wire;

a second blocking capacitor connected between said positive input and said second wire;

a feedback resistor connected between said negative input and said output; and

said positive input connected to said voltage reference source.

21. A digital signaling interface circuit as claimed in claim 17, wherein there is further included sources of first and second reference voltages, said signal slicing means comprising:

first and second comparators each having first and second inputs, said second input of said first comparator connected to said first input of said second comparator and to said common mode noise rejection receiver;

said first input of said first comparator and said second input of said second comparator being connected to said first and second source of said reference voltages, respectively;

said first comparator being operative to provide a first comparator signal when said receiver signal exceeds said first reference voltage, said second comparator being operative to provide a second comparator signal when said receiver signal is less than said second reference voltage;

whereby said digital interface signals of first, second and third characteristics are represented by said first comparator signal, said second comparator signal, and an absence of said first and second comparator signals, respectively.

22. A digital signaling interface circuit as claimed in claim 21, wherein:

there is further included, first and second feedback resistors connected across the output and second input of each comparator.

23. A digital signaling interface circuit as claimed in claim 17, wherein there is a voltage reference isolation capacitor connected between said common mode noise rejection receiver and said signal slicing means.

24. A digital signaling interface circuit as claimed in claim 13, wherein said filter means comprises first and second series connected filter resistors connected between said first coupling capacitor and the base of said first transistor;

a first capacitor connected between the emitter of said first transistor and the junction of said first and second filter resistors; and

a second capacitor connected between the base of said first transistor and the emitter of said second transistor.