Line support processor for data transfer system

• US 4,494,194 A
• Filed: 09/30/1982
• Issued: 01/15/1985
• Est. Priority Date: 09/30/1982
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Corp (Unisys Corporation)
• Inventors: Harris, Craig W., Jevons, Lyle O. Jr., Loskorn, Richard A.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Niessen, William G.
• Application Number:
  US06/430,575
• Time in Patent Office: 838 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/46
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

Data transfers between remote data sets, data terminals and a main host computer are controlled by a peripheral-controller designated as a Line Support Processor (LSP). The LSP manages a plurality of line adapters, each of which handles a separate data comm line. The LSP includes internal processor means and interface circuit means to effectuate data transfer operations using a variety of protocols and systems both for bit-oriented and byte-oriented data transfers.

Claims

1. In a data-comm subsystem wherein a line support processor controls data transfer operations between a host computer and remote data terminals, and said line support processor includes a plurality of line adapters, a data link interface unit and a microprocessor, said microprocessor including program data in an internal PROM and in external RAM storage means and having an I/O bus and output control registers providing control data and information data to said line adapters, said line support processor comprising:

(a) a plurality of line adapters, operatively controlled by said microprocessor, and wherein each line adapter includes;

(a1) USART control component means for transmission of or reception of data between a remote terminal and said microprocessor;

(a2) timing means for setting baud rate of data transfers and for protocol timing signals;

(a3) gating means, connected to said USART control component means and said timing means, for signaling said microprocessor for service, and for activating a discrete bit line of said I/O bus;

(a4) designate logic means, receiving control signals from said gating means and from said microprocessor, for selecting a particular line adapter and a particular register in said USART means or said timing means;

(b) said microprocessor operating to enable a data transfer path from a requesting USART/timing means to said I/O bus for transfer of data to said microprocessor and including;

(b1) means to scan said I/O bus lines to identify the activated bit line which designates a particular line adapter;

(b2) means to select which input line of each of a plurality of multiplexors will be connected for throughput;

(c) said enabled data transfer path including;

(c1) driver-controller bus means for connecting a selected USART/timing means via a data transfer bus to a group of said multiplexors for data transfer to said microprocessor;

(c2) a data transfer bus connected to a group of n said multiplexors for parallel-transfer of n bits of data;

(c3) a plurality of groups of said multiplexors wherein each group of n said multiplexors connects n bits from said data transfer bus to said I/O bus.

2. In a data-comm subsystem wherein a line support processor controls data transfer operations between a host computer and remote data terminals, and said line support processor includes a plurality of line adapters, a data link interface unit and a microprocessor, said microprocessor including program data in an internal PROM and in external RAM storage means and having an I/O bus and output control registers providing control data and information data to said line adapters, said line support processor comprising:

(a) a plurality of line adapters, operatively controlled by said microprocessor, and wherein each line adapter includes;

(a1) programmable USART control component means for transmission of or reception of data between a remote terminal and said microprocessor, said USART means including a plurality of component control registers;

(a2) programmable timing means for setting baud rate of data transfers and for protocol timing signals, said timing means including a plurality of timing control registers;

(a3) gating means, connected to said USART control component means and said timing means, for signaling said microprocessor for service, and for activating a discrete bit line of said I/O bus;

(a4) designate logic means, receiving control signals from said gating means and from said microprocessor, for selecting a particular line adapter;

(b) said microprocessor operating to identify one of said USART component means or said timing means requiring service by scanning for an activated bit line of said I/O bus, and for reading out data from said USART means or timing means into said microprocessor in order to determine new instructions to be required, said microprocessor including;

(b1) output select control signals connected to each of a plurality of multiplexors for selecting one of a plurality of input signals;

(c) bidirectional driver means, controlled by said microprocessor, for routing data from said microprocessor to a selected line adapter, or for routing data from a selected line adapter to one of a selected set of multiplexors to enable read out of data to said microprocessor from said selected line adapter;

(d) select-connection means for receiving a plurality of information signals and for connecting selected ones of said information signals to selected bit-lines of said I/O bus, said select-connection means including;

(d1) a plurality of four groups of multiplexors, each group of multiplexors having "n" multiplexors and each group connected to service a given line adapter such that the output of each one of said "n" multiplexors connects to a discrete bit line of said I/O bus and each multiplexor is connected to receive a plurality of input signals including data signals from a line adapter via said bidirectional driver means, where "n" represents the number of bit lines which can parallel-transfer a byte of data;

(d2) means to receive control signals from said microprocessor for selecting which one of said plurality of input signals is to be connected to said I/O bus;

(e) I/O bus means connected to each of said plurality of groups of multiplexors and to said microprocessor such that each output line of each group of multiplexors has a discrete connection to a separate bit line of said I/O bus.

3. A line support processor for controlling data communication lines which transfer data between a host computer and a plurality of data-terminals, said line support processor comprising:

(a) interface circuit means connecting said host computer with an internal processor means and a line adapter means, and functioning to regulate data transfer between said host computer and said line adapter means under control of said internal processor means;

(b) said internal processor means, initiated by commands from said host computer, for controlling operations of said line adapter means and said interface circuit means, said internal processor means connected to said interface circuit means and said line adapter means;

(c) said line adapter means including one or more line adapters wherein each line adapter controls data transfer operations between itself and one data terminal connected by a data-comm line, said line adapter means being controlled by said internal processor means, and wherein at least one of said line adapters is connected to an automatic calling unit, and wherein each of said line adapters includes;

(c1) control-and-register means, responsive to commands from said internal processor means, for transmission of or reception of data from a connected data terminal;

(c2) timing and register means, responsive to commands from said internal processor means, for setting the baud rate of data transfer and for setting protocol timing signals;

(c3) means for routing data from said internal processor means to said control-and-register means and said timing-and-register means, or for routing data from said control-and-register means to a multiplexor means;

(c4) jumper identification means for setting a line adapter identifying signal;

(d) said multiplexor means for receiving control data and information-transfer-data for transmittal to said internal processor means, said multiplexor means including;

(d1) input signals from said jumper identification means to identify a particular line adapter as bit-oriented or byte-oriented, and to identify the data-comm line as either a private line or a switched line, and to identify the line adapter as having or not having an automatic calling unit;

(d2) input signals from said attached automatic calling unit for providing information data, to said processor means, regarding the operating status of said automatic calling unit;

(d3) input signals for conveying data from either of a selected one of said control-and-register means or said timing-and-register means;

(d4) input signals from a selected one of said control-and-register means or said timing-and-register means to request service from said processor means.