Balanced system for ranging and synchronization between satellite pairs

• US 4,494,211 A
• Filed: 11/24/1982
• Issued: 01/15/1985
• Est. Priority Date: 11/24/1982
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Schwartz, Jay W.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Harkcom, Gary V.
• Application Number:
  US06/444,139
• Time in Patent Office: 783 Days
• Field of Search: 364/131-132, 364/143, 364/183, 364/569, 364/571, 343/55 M, 343/6.5 R, 343/7 R, 343/17.7, 343/352, 343/356, 343/358, 343/367, 73/6, 371/20, 371/4, 375/107-110, 368/46-47
• US Class Current: 375/356
• CPC Class Codes: G01S 11/08 using synchronised clocks
• CPC Class Codes: G04G 7/02 by radio
• CPC Class Codes: H04B 7/2125 Synchronisation
• CPC Class Codes: H04J 3/0676 Mutual

Abstract

A balanced ranging and synchronization (R&S) system for a master(M)-slave satellite pair including a clock, a transmitter, a receiver, a time difference measuring device and a calculating device on both M and S. Each satellite transmits timing signals synchronized to its clock, receives the timing signals from the other satellite and measures the time difference between the transmission and reception of the timing signals. The time difference measured on each satellite is then transmitted to the other satellite. The caluculating device on each satellite utilizes these time difference measurements to calculate the asynchronism between the clocks and the range between the satellites. Finally the S clock is adjusted so that the asynchronism is reduced to within predetermined limits.

Claims

1. A balanced ranging and synchronization (R &

S) system for synchronizing a clock on a slave platform (S) to a master platform (M) and for measuring the distance between M and S comprising;

an M clock, positioned on M, for generating an M clock output signal;

an S clock, positioned on S, for generating a S clock output signal;

M signal transmitting means on M, interconnected with said M clock, for transmitting an M timing signal in response to a predetermined M clock output signal;

S signal transmitting means on S, interconnected with said S clock, for transmitting an S timing signal in response to a predetermined S clock output signal;

M receiving means on M for receiving signals, including said S timing signal, from S;

S receiving means on S for receiving signals, including said M timing signal, from M;

M time difference measuring (TDM) means, interconnected with said M clock and said M receiving means, for measuring the M time difference between the transmission of said M timing signal and the reception of said S timing signal and for encoding said M time difference in an M time difference output signal;

S time difference measuring (TDM) means, interconnected with said S clock and said S receiving means, for measuring the S time difference between the transmission of said S timing signal and the reception of said M timing signal and for encoding said S time difference in an S time difference output signal;

S calculating means, interconnected with said S TDM means, said S receiving means and said S clock and with inputs including said M and S time difference output signals, for calculating the asynchronism between said M clock and said S clock, and for generating an S clock adjusting output signal for advancing or retarding said S clock so that said S clock is synchronized with said M clock.

2. The balanced R &

S system, recited in claim 1, wherein;

said M clock is a first digital counter interconnected with a first stable quartz oscillator; and

said S clock is a second digital counter interconnected to a second stable quartz oscillator.

3. The R &

S system recited in claim 2 wherein;

said M TDM measuring means is an M TDM digital clock for generating an M time difference word (TDW); and

said S TDM measuring means is an S TDM digital clock for generating an S TDW.

4. The R &

S system recited in claim 3 with said M signal transmitting means including;

an M multiplexer (MUX), interconnected with said M TDM clock, for formatting a data stream transmitted between M and S into frames where each frame is started by a start-of-frame word (SOF_iM) generated at time T_iM and each frame includes a Frame ID word and an M TDW, and for starting said M TDM clock when said SOF_iM is generated; and

with said S signal transmitting means including;

an S multiplexer (MUX), interconnected with said S TDM clock, for formatting a data stream transmitted between S and M into frames where each frame is started by a start-of-frame word (SOF_iS) generated at time T_iS and each frame includes a Frame ID word and a S TDW and for starting said S TDM clock when said SOF_iS is generated.

5. The R &

S system recited in claim 4 with said M receiving means including;

an M demultiplexer (DEMUX) for stopping said M TDM clock when said SOF_iS is received at time (T_iS)_M ; and

an M demodulator; and

with said S receiving means including;

an S DEMUX for stopping said S TDM clock when said SOF_iM is received at time (T_iM)_S ; and

an S demodulator.

6. The R &

S system recited in claim 5 further comprising;

S compensating means interconnecting said S modulator with said S demodulator and M compensating means interconnecting said M modulater with said M demodulater, said S and M compensating means for stabilizing the equipment delay times in said R &

S system.

7. The R &

S system recited in claim 6 wherein;

said data stream from M to S is carried by an M laser beam generated by an M laser; and

said data stream from S to M is carried by an S laser beam generated by an S laser.

8. A balanced ranging and synchronization (R &

S) system for synchronizing a clock on a slave platform (S) to a master platform (M) and for measuring the distance between M and S comprising;

an M clock, positioned on M, for generating an M clock output signal;

an S clock, positioned on S, for generating a S clock output signal;

M signal transmitting means on M, interconnected with said M clock, for transmitting an M timing signal in response to a predetermined M clock output signal;

S signal transmitting means on S, interconnected with said S clock, for transmitting an S timing signal in response to a predetermined S clock output signal;

M receiving means on M for receiving signals, including said S timing signal, from S;

S receiving means on S for receiving signals, including said M timing signal, from M;

M time difference measuring (TDM) means, interconnected with said M clock and said M receiving means, for measuring the M time difference between the transmission of said M timing signal and the reception of said S timing signal and for encoding said M time difference in an M time difference output signal;

S time difference measuring (TDM) means, interconnected with said S clock and said S receiving means, for measuring the S time difference between the transmission of said S timing signal and the reception of said M timing signal and for encoding said S time difference in an S time difference output signal;

S calculating means, interconnected with said S TDM means said S receiving means and said S clock and with inputs including said M and S time difference output signals, for calculating the asynchronism between said M clock and said S clock;

according to the formula ##EQU2## and for calculating the time delay in the free space channel between M and S according to the formula;

##EQU3## where T_iS is the true time when the predetermined S clock output signal is generated,

T_iM is the true time when the predetermined M clock output signal is generated,

τ

_iS is the time delay encoded in the S time difference output signal,

τ

_iM is the time delay encoded in said M time difference output signal;

d_r is the time equipment delay in the channel between S and M,

d_f is the equipment delay in the channel between M and S, said S calculating means also for generating a clock adjusting output signal for advancing or retarding said S clock so that said S clock is synchronized with said M clock.

9. The balanced R &

S system, recited in claim 8, wherein;

said M clock is a first digital counter interconnected with a first stable quartz oscillator; and

said S clock is a second digital counter interconnected to a second stable quartz oscillator.

10. The R &

S system recited in claim 9 wherein;

said M TDM measuring means is an M TDM digital clock for generating an M time difference word (TDW); and

said S TDM measuring means is an S TDM digital clock for generating an S TDW.

11. The R &

S system recited in claim 10 with said M signal transmitting means including;

an M multiplexer (MUX), interconnected with said M TDM clock, for formatting a data stream transmitted between M and S into frames where each frame is started by a start-of-frame word (SOF_iM) generated at time T_iM and each frame includes a Frame ID word and an M TDW, and for starting said M TDM clock when said SOF_iM is generated; and

with said S signal transmitting means including;

an S multiplexer (MUX), interconnected with said S TDM clock, for formatting a data stream transmitted between S and M into frames where each frame is started by a start-of-frame word (SOF_iS) generated at time T_iS and each frame includes a Frame ID word and a S TDW and for starting said S TDM clock when said SOF_iS is generated.

12. The R &

S system recited in claim 11 with said M receiving means including;

an M demultiplexer (DEMUX) for stopping said M TDM clock when said SOF_iS is received at time (T_iS)_M ; and

an M demodulator; and

with said S receiving means including;

an S DEMUX for stopping said S TDM clock when said SOF_iM is received at time (T_iM)_S ; and

an S demodulator.

13. The R &

S system recited in claim 12 further comprising;

S compensating means interconnecting said S modulator with said S demodulator and M compensating means interconnecting said M modulater with said M demodulater, said S and M compensating means for stabilizing the equipment delay times in said R &

S system.

14. The R &

S system recited in claim 13 wherein;

said data stream from M to S is carried by an M laser beam generated by an M laser; and

said data stream from S to M is carried by an S laser beam generated by an S laser.

15. A balanced ranging and synchronization (R &

S) system for synchronizing the clock on a slave platform (S) to a master platform (M) and for determining the range between M and S where M and S are transfering high-rate digital data therebetween said R &

S system comprising;

an M clock including an M stable oscillator and an M digital counter for providing an M digital clock output signal; and

an S clock including an S stable oscillator and an S digital counter for providing an S digital clock output signal;

M multiplexing means interconnected with said M clock for formatting an M digital data stream transmitted from M to S into frames where each frame is started by an M start-of-frame word (SOF_iM) generated at time T_iM by said M multiplexing means upon receiving a predetermined M digital clock output signal;

S multiplexing means, interconnected with said S clock for formatting an S digital data stream transmitted from S to M into frames where each frame is started by an S SOF_iS generated at time T_iS by said S multiplexing means upon receiving a predetermined S digital clock output signal;

M demultiplexing means for receiving said SOF_iS transmitted from S, where said SOF_iS is received at time (T_iS)_M ;

S demultiplexing means for receiving said SOF_iM transmitted from M where said SOF_iM is received at (T_iM)_S ;

M TDM means, interconnected with said M clock and said M demultiplexer means where said M TDM includes an M TDM digital clock for measuring the time interval between the time said SOF_iM is generated, T_iM, and the time said SOF_iS is received, (T_iS)_M, where the output of said M TDM means is an M time difference word (TDW) and where said M TDW is included in the digital data stream transmitted from M to S;

S TDM means, interconnected with said S clock and said S demultiplexer, where said S TDM includes an S TDM digital clock for measuring the time interval between the time said SOF_iS is generated, T_iS, and the time said SOF_iM is received, (T_iM)_S, where the output of said S TDM means is an S time difference word (TDW) and where said S TDW is included in the digital data stream transmitted from S to M;

S calculating means, interconnected with said S clock and with inputs including said S TDW from said S TDW means and said M TDW transmitted to S from M, for calculating the asynchronism between said S clock and said M clock and for calculating the intersatellite range;

M calculating means, interconnected with said M clock and with inputs including said M TDW and said S TDW transmitted from S, for calculating the asynchronism and range, where said M and S calculating devices calculate the asynchronism according to the formula ##EQU4## and the time delay in the free space channel between M and S according to the formula, ##EQU5## where T_iS is the true time when the predetermined S clock output signal is generated,

T_iM is the true time when the M predetermined M clock output signal is generated,

τ

_iS is the time delay encoded in the S TDW,

τ

_iM is the time delay encoded in the M TDW,

d_r is the equipment delay in the channel between S and M,

d_f is the equipment delay in the channel between M and S, said S calculating means also for generating a clock adjusting output signal for advancing or retarding said S clock so that said S clock is synchronized with said M clock.

16. The R &

S system recited in claim 15 wherein;

said S calculating means is a microprocessor for calculating Δ

T_i and R, and for generating said clock adjusting signal.

17. The R &

S system recited in claim 15 wherein;

said high-rate digital data transferred to S from M is carried by an M laser beam generated by an M laser; and

wherein;

said high-rate digital data transferred to M from S is carried by an S laser beam generated by an S laser.