Time division switching system for circuit mode and packet mode channels

• US 4,494,231 A
• Filed: 01/15/1982
• Issued: 01/15/1985
• Est. Priority Date: 01/23/1981
• Status: Expired due to Fees

• Current Assignee: Jean L. Dauphin, Olivier F. Louvet, Serge Slawy
• Original Assignee: Jean L. Dauphin, Olivier F. Louvet, Serge Slawy
• Inventors: Slawy, Serge, Louvet, Olivier F., Dauphin, Jean L.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/339,880
• Time in Patent Office: 1,096 Days
• Field of Search: 370/60, 370/91, 370/92, 370/94, 370/79, 370/84
• US Class Current: 370/352
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04M 11/068 using time division multiplex techniques; integrated services digital networks H04Q11/0428

Abstract

The switching network included in the system is connected to circuit mode and/or packet mode mono- or multi-channel digital lines via connection modules. These modules enable the system connections to be standardized and accept thus any number of multiplexed channels in the lines and any transmission mode, namely duplex or half-duplex. The flag/packet transition in a packet mode channel is detected in a connection module and is transmitted as a particular word in a predetermined time interval of the outgoing multiplex of this module, at the same time as the address of the channel, thereby precluding the use of purpose-built links.

Claims

1. A time division digital switching system for switching channels with a predetermined rate, said channel having circuit mode channels and packet mode channels conveying useful information words with a predetermined number of bits, said system comprising:

G first multiplexing means, each multiplexing a group of I reception channels into an outgoing multiplexed signal, G first demultiplexing means each demultiplexing an incoming multiplexed signal into a group of I emission channels, of said multiplexed signals having a recurrent frame including I useful information words assigned to said multiplexed channels, where G and I are integers greater than one; and

means for bidirectionally switching said circuit mode channels and said packet mode channels between lines carrying said incoming and outgoing multiplexed signals;

each of said first multiplexing means comprising;

means for introducing working information words into predetermined time intervals, each of the information words defining a multiframe and being included in one of I consecutive frames of said outgoing multiplexed signal words, each of said information words having said predetermined number of bits respectively assigned to said I reception channels, said incoming multiplexed signals also conveying said frames and multiframes; and

means for detecting flag/packet transitions in said packet mode reception channels to replace the working information word by a flag/packet transition indicating word in a frame of said outgoing multiplexed signal having the same rank in the multiframe as that in said packet mode reception channel in which a flag/packet transition has been detected;

said switching means comprising means receiving the working information words multiplexed in the multiframes of said outgoing multiplexed signals for detecting the transition indicating word to switch the channel having a detected transition over to a free packet mode channel in an incoming multiplexed signal.

2. A time division digital switching system as claimed in claim 1, wherein said transition detecting means includes means for introducing, in conjunction with said flag/packet transition indicating word, the address of said channel in which a transition is detected, in place of the corresponding working information word in said outgoing multiplexed signal, and wherein said transition indicating word detecting means includes means for reading said channel address in response to the detection of said flag/packet transition indicating word.

3. A time division digital switching system as claimed in claim 1 or 2, wherein each of said channels conveys useful information words and working information words;

wherein each of said first multiplexing means comprises means for multiplexing said I reception channels into an outgoing useful information multiplex which is applied to means for introducing useful information words into said frame of said outgoing multiplexed signal and to said flag/packet transition detecting means, and into an outgoing working information multiplexed signal which is applied to said working information word introducing means; and

wherein each of said demultiplexing means comprises means for separating the useful information words within said incoming multiplexed signal into an incoming useful information multiplexed signal, means for separating the working information words within said incoming multiplexed signal into an incoming working information multiplexed signal, and means for demultiplexing said incoming useful and working information multiplexed signal into said emission channels.

4. A time division digital switching system as claimed in claim 3 wherein said working information words for each channel comprise a circuit mode or packet mode indicating word.

5. A time division digital switching system as claimed in claim 4 wherein said mode indicating word also indicates the type of device which emitted the useful information, such as a subscriber equipment, a circuit mode, or packet mode outside the switching network or a packet switching unit.

6. A time division digital switching system as claimed in claim 4 wherein each of said first demultiplexing means comprises means connected to be responsive to said incoming multiplexed signal for detecting the mode indicating word to control the replacement of said mode indicating word in a working information word relative to a corresponding reception channel in said outgoing multiplexed signal of said first multiplexed means of the same group by the flag/packet transition indicating word when a flag/packet transition in the reception channel is detected by said transition detecting means, the mode indicating detecting means being activated after said packet mode indicating word in a working information word relative to an incoming multiplex emission has been detected in said incoming multiplexed signal.

7. A time division digital switching system as claimed in claim 6 wherein, in each channel, said useful and working information words are grouped into pairs and multiplexed bit-by-bit in a frame, and wherein said outgoing and incoming useful information multiplexed signals convey in said predetermined number, a recurrent series of same-rank bits of said useful information words whilst said outgoing and incoming working information multiplexed signal convey in said predetermined number, a recurrent series of same-rank bits of said working information words.

8. A time division digital switching system as claimed in claim 7, wherein

said means for introducing useful and working information words into said outgoing multiplexed signals comprises a memory having at least two sub-memories, said incoming bit series in said predetermined number being written row by row in one of said sub memories during a frame, and said I useful information words being read column by column in another sub-memory, the information words read column by column respectively being said working information word of said reception channel having the same rank in the frame as that of said frame in said multiframe;

and

said means for separating said useful and working information words in said incoming multiplexed signal including a memory having at least two sub-memories, said I useful information words being written row by row in one of said separating means sub-memories during said frame and said outgoing bit series in said predetermined number being read column by column in another separating means sub-memory, said I useful information words being respectively said working information word of said emission channel having the same rank in the frame as that of said frame in said multiframe; and

reciprocally during the following frame or a frame of predetermined rank.

9. A time division digital switching system as claimed in claim 8 wherein said mode indicating word detecting means comprises means for imposing a delay of at least one consecutive frame between writing and reading a useful information word of a packet mode channel in said memory of said useful information word introducing means after said packet mode indicating word has been detected in an incoming multiplexed emission working information word relative to the corresponding emission channel, and wherein said memory of said useful information word introducing means comprises at least three sub-memories which are cyclically written during three consecutive frames and having columns which read with a delay of at least one or two frames depending on whether the read column relates to a circuit mode channel word or a packet mode channel word.

10. A time division digital switching system as claimed in claim 1 wherein each pair of first multiplexing and demultiplexing means relating to a group of I channels is linked via second multiplexing and demultiplexing means to circuit mode and packet mode information multi-channel bidirectional digital lines, the sum of said channels of said lines being equal at the most to the integer I,

wherein in each of said line channels are successively included an address word of said channel, at least one bit of a working information word and a useful information word;

wherein said second multiplexing and demultiplexing means comprises, for each line;

at the reception end;

means for detecting said channel address words,

means for demultiplexing said useful information words and said working information bits at the respective rates thereof for each channel, and

means for multiplexing the useful information words and the working information word into a reception channel of said line in which the useful and working information words are multiplexed bit by bit; and

respectively at the emission end;

means for demultiplexing each emission channel of said line into said useful information words and said working information bits at the respective rates thereof,

means for multiplexing said useful information words and said working information bits at the respective rates thereof of all said channels into said line channels, and

means for inserting said address words in said multiplexed channels at the output of the latter multiplexing means.

11. A time division digital switching system as claimed in claim 10, wherein said second multiplexing and demultiplexing means of each line comprises means connected between the line and said channel address word detecting and inserting means for connecting and electrically matching the duplex or half-duplex transmission mode of said line.

12. A time division digital switching system as claimed in claim 11, wherein, when the line is in said half-duplex transmission mode, each elementary cycle of said half-duplex mode includes means for emitting and then receiving the information block of a single channel, the total half-duplex cycle comprising a number of said elementary cycles equal to the number of said multiplexed channels in said line.

13. A time division digital switching system as claimed in one of claim 11 or 12 wherein at least two useful information words are packetized in each channel.

14. A time division digital switching system as claimed in claim 10, 11 or 12 further including means for connecting to each first multiplexing and demultiplexing means related to at least one line, such as one half-duplex line or a duplex line, and to at least one line such as monochannel line or a line with two or more multiplexed channels.

15. A time division digital switching system as claimed in claim 10, 11 or 12 wherein each assembly of said first and second multiplexing and demultiplexing means related to a pair of incoming and outgoing multiplexed signals are contained in a module having means on the line side for a column with I locations each corresponding to second multiplexing and demultiplexing means for monochannel lines, said second multiplexing and demultiplexing means for a line with K channels occupying all or part of K adjacent locations, where K is an integer greater than one.

16. A time division digital switching system as claimed in claim 10, 11 or 12 wherein the working information and useful information rates in a line channel are in a ratio of 1/M8, where M is an integer.

17. A time division digital switching system as claimed in claim 1, wherein said first multiplexing and demultiplexing means of each group comprise means for introducing an alignment word in each frame of said outgoing multiplexed signal and means for detecting an alignment word in each frame of said incoming multiplexed signal in order to locally synchronize timing means of said first multiplexing and demultiplexing means with timing means of said switching means;

each frame of said incoming and outgoing multiplexed signals comprising an alignment word, a working information word and I useful information words.