Biasing method for improved performance in field effect devices

• US 4,496,909 A
• Filed: 02/28/1983
• Issued: 01/29/1985
• Est. Priority Date: 01/18/1979
• Status: Expired due to Fees

• Current Assignee: Lawrence Kavanau
• Original Assignee: Lawrence Kavanau
• Inventors: Knapp, Richard P.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US06/470,522
• Time in Patent Office: 701 Days
• Field of Search: 330/149, 330/277, 330/296, 307/304
• US Class Current: 330/277
• CPC Class Codes: H03F 3/165 with junction-FET's

Abstract

A biasing method to obtain improved performance of Field Effect Devices is disclosed. In accordance with the method, the nominal operating point for a Field Effect Device is chosen so that the electric field in the drain depletion region is biased in the carrier partial velocity saturation regime. With this biasing, the transconductance and output conductance of the field effect device have the same current dependence so that the ratio of these two parameters is independent of current. Thus the gain of the device is independent of bias source noise so that the bias source noise does not modulate the input signal. In addition, if a device is biased in accordance with the present invention, the drain noise modulation of the edge of the drain depletion zone emulates that created by a gate input, so that the depletion zone noise may be considered as a gate input noise, and the transconductance is not intermodulated by that noise. Accordingly, the output of the device is substantially free of noise intermodulation components and has maximum coherence with an equivalent gate input so as to both minimize the noise output by the field effect device and allow maximum reduction of the noise when using feedback.

Claims

1. A method of minimizing transistor by noise, the field effect transistor having a gate, source and drain comprising setting the quiescent bias point of the field effect transistor by setting the gate to source voltage and the drain to source voltage to operate the transistor in the current saturation region with an electric field in a drain depletion zone such that the carrier velocity is in the partial carrier velocity saturation zone to provide a carrier drift velocity approximately proportional to the square root of the electric field to distort the output conductance functional with current to substantially match the transconductance functional with current to substantially match the transconductance functional with current, thereby linearizing the voltage transfer function of the device, defined A_v =g_m /g_o, where g_m is the transconductance and go is the output conductance of the field effect transistor.

2. The method of claim 1 wherein the average electric field in the drain depletion zone is set substantially in the center of the partial carrier velocity saturation zone to minimize the distortion of the linearizing bias condition with changes in voltage and current about their respective quiescent bias points.

3. A method of minimizing cross modulation of the transconductance of a field effect transistor by noise, the field effect transistor having a gate, source and drain comprising setting the quiescent values of the gate to source and the drain to source voltages of the transistor so that the drain current dependence of the output conductance go of the transistor substantially matches the drain current dependence of the transconductance g_m of the transistor. whereby the voltage transfer function A_v =g_m /g_o is substantially independent of drain current, thereby reducing the modulation of the transconductance by the drain noise voltage.

4. A field effect transistor having improved transconductance coherence comprising a field effect transistor having a source, gate and drain, and a biasing means coupled to said field effect transistor to determine the quiescent values of the gate to source voltage and the drain to source voltage on said transistor, said biasing means being a means for setting the gate to source voltage and the drain to source voltage to operate the transistor in the current saturation region with an electric field in the drain depletion zone such that the carrier velocity is in the partial carrier velocity saturation zone to provide a carrier drift velocity approximately proportional to the square root of the electric field to distort the output conductance functional with current to substantially match the transconductance functional with current, thereby linearizing the voltage transfer function of the device, defined A_v =g_m /g_o where g_m is the transconductance and g_o is the output conductance of the field effect transistor.

5. A field effect transistor having improved transconductance coherence comprising a transistor having a source, gate and drain, and a biasing means coupled to said field effect transistor to determine the quiescent values of the gate to source voltage and the drain to source voltage on said transistor, said biasing means being a means for setting the quiescent values of the gate to source and the drain to source voltage of the transistor so that the drain current dependence on the output conductance (g_o) of the transistor substantially matches the drain current dependence of the transconductance (g_m) of the transistor, whereby the voltage transfer function A_v =g_m /g_o is substantially independent of drain current.