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Interrupt processor

  • US 4,498,136 A
  • Filed: 12/15/1982
  • Issued: 02/05/1985
  • Est. Priority Date: 12/15/1982
  • Status: Expired due to Term
First Claim
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1. In a data processor, an interrupt processor instruction pipeline having a sequence of instruction stages which sequentially process a machine instruction in respective sequential machine cycles, output from an instruction store, comprising:

  • an interrupt class decoder having an input connected to the output of said instruction store, for decoding each said machine instruction into an interrupt class and outputting a signal on a corresponding one of a plurality of interrupt class output lines;

    an interrupt sequence detector pipeline having a sequence of staging registers which are connected to said interrupt class output lines and which are sequentially gated in synchronism with said instruction stages of said instruction pipeline, for sequentially propagating a non-interruptible sequence indicator bit to an output line;

    a register having a data input connected to an interrupt signal line, a control input connected to said output of said interruptible sequence detector pipeline and an output connected to said instruction pipeline, for storing an interrupt signal when said noninterruptible sequence detector bit is input to said control input thereof, said interrupt signal being passed to said instruction pipeline when said detector bit is absent from said control input;

    whereby interruptions of said instruction pipeline can be selectively inhibited in response to said interrupt classes of said machine instructions in said instruction pipeline.

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