Heterojunction Schottky gate MESFET with lower channel ridge barrier

• US 4,499,481 A
• Filed: 09/14/1983
• Issued: 02/12/1985
• Est. Priority Date: 09/14/1983
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Greene, Richard F.
• Primary Examiner(s): Clawson, Jr., Joseph E.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/532,122
• Time in Patent Office: 517 Days
• Field of Search: 357/16, 357/55, 357/15, 357/22, 357/22 S, 357/20, 357/23.4, 357/22 P
• US Class Current: 257/194
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT

Abstract

An FET with an extremely short channel formed by the apex of a substrate ridge structure protruding upward through the channel layer toward a Schottky-barrier gate contact. The device is formed by etching a modulation-doped substrate to form an upwardly protruding ridge with the apex modulation-doped. A semiconductor layer is then disposed over the substrate surface with the protruding ridge to obtain an epitaxial interface therebetween. Source and drain regions are doped into the semiconductor layer on opposite sides of the ridge structure. Finally, ohmic contacts are formed on the semiconductor layer over the source and drain regions and a Schottky-barrier metalization is deposited on the semiconductor layer above the ridge structure. This device has a very short channel, a low transit time, a low gate capacitance, and an enhanced transconductance.

Claims

1. A semiconductor switching device including in combination:

a doped semiconductor substrate of the first conductivity type and of a first material with one surface thereof being approximately flat but with a ridge structure rising from a portion of said flat surface;

a semiconductor layer of a second material disposed over the flat surface and ridge structure of said substrate to form an epitaxial heterojunction interface therewith, heavily doped source and drain regions of the first conductivity type being formed down into said semiconductor layer on opposite sides of said ridge structure;

source and drain ohmic contacts being disposed on said semiconductor layer above said source and drain regions;

a gate material being disposed on said semiconductor layer above said substrate ridge structure to form a barrier with said semiconductor layer.

2. A switching device as defined in claim 1, wherein a portion of said ridge structure is modulation doped.

3. A switching device as defined in claim 2, wherein said modulation doped portion of the ridge structure is the area around the apex of the ridge structure.

4. A switching device as defined in claim 3, wherein said gate material is Schottky-barrier material.

5. A switching device as defined in claim 4, wherein said ridge structure is formed by an approximately V-shaped ridge.

6. A switching device as defined in claim 5, wherein said semiconductor substrate is AlGaAs with n-type dopants.

7. A switching device as defined in claim 6, wherein said semiconductor layer is GaAs and said source and drain regions are doped with n-type dopants.

8. A switching device as defined in claim 2, wherein said modulation-doped portion of the ridge structure comprises an outer layer following the profile of said ridge structure.

9. A field-effect transistor including in combination:

a semiconductor substrate of the first conductivity type and of a first material with one surface thereof being approximately flat but with a ridge structure rising from a portion of said flat surface, said ridge structure being modulation-doped along an edge portion thereof;

a semiconductdor layer of a second material disposed over the flat surface and ridge structure of said substrate to form an epitaxial heterojunction interface therewith, heavily doped source and drain regions of the first conductivity type being formed in said semiconductor layer on opposite sides of said ridge structure essentially down to said substrate.

source and drain ohmic contacts being disposed on said semiconductor layer above said source and drain regions; and

a Schottky-barrier material being disposed on said semiconductor layer above said substrate ridge structure to form a gate contact.

10. An FET as defined in claim 9, wherein said portion of said ridge structure which is modulation doped is the apex area thereof.

11. An FET as defined in claim 10, wherein said substrate ridge structure rises from said flat surface to form an approximate V-shaped ridge.