Signal transfer timing control using stored data relating to operating speeds of memory and processor

• US 4,499,536 A
• Filed: 12/09/1981
• Issued: 02/12/1985
• Est. Priority Date: 12/17/1980
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Gemma, Kazutoshi, Ishibashi, Michiyasu
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): WILLIAMS JR, ARCHIE E
• Application Number:
  US06/329,048
• Time in Patent Office: 1,161 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/167
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A memory controlling apparatus retains time information prepared based on performance of a memory and a processor, and determines timing of signal exchange between the memory and the processor based on the time information. An access time to the memory is reduced while maintaining a flexibility to a change of the access time due to increase of memory capacity or reconfiguration of the memory.

Claims

1. A memory controlling apparatus for controlling signal transfer between a memory for storing data and a processor for processing the data accessed to said memory, comprising:

means for retaining time information based on the operating speed of at least said memory and said processor, including means for receiving from said processor and storing respective data relating to the operating speed of said processor and the operating speed of said memory; and

control means for controlling the timing of signal transfer between said processor and said memory based on at least said time information of said retaining means, including first means responsive to said processor for transmitting a memory access signal to said memory and second means connected to said receiving and storing means and responsive to said access signal for transmitting to said memory a signal to command said memory to transmit data to said processor at a time subsequent to transmission of said memory access signal which is determined by said data relating to the operating speed of said memory and said processor as stored in said receiving and storing means.

2. A memory controlling apparatus according to claim 1 wherein said control means comprises means for controlling said timing of said signal transfer based on said time information and the type of access to said memory.

3. A memory controlling apparatus according to claim 1 wherein said receiving and storing means comprises means for storing the access time of the memory cells of said memory and information concerning the machine cycle time of said processor.

4. A memory controlling apparatus according to claim 2, wherein said receiving and storing means comprises means for storing the access time of memory cells of said memory and information concerning the machine cycle time of said processor.

5. A memory controlling apparatus according to claim 1 wherein said second means in said control means comprises counter means for counting signals generated in synchronism with a machine cycle of said processor and means responsive to the output of said counter means and the output of said first means for producing said signal to command said memory to transmit data when the count of said counter means reaches a predetermined count in relation to the data relating to the operating speed of said memory and said processor as stored in said receiving and storing means.

6. A memory controlling apparatus according to claim 2, wherein said second means in said control means comprises counter means for counting signals generated in synchronism with a machine cycle of said processor and means responsive to the output of said counter means and the output of said first means for producing said signal to command said memory to transmit data when the count of said counter means reaches a predetermined count in relation to the data relating to the operating speed of said memory and said processor as stored in said receiving and storing means.

7. A memory controlling apparatus according to claim 5, wherein said receiving and storing means comprises means for storing the access time of the memory cells of said memory and information concerning the machine cycle time of said processor.

8. A memory controlling apparatus according to claim 6, wherein said receiving and storing means comprises means for storing the access time of the memory cells of said memory and information concerning the machine cycle time of said processor.

9. A memory controlling appartus according to claim 5, wherein said first means in said control means comprises logic circuit means for producing output control signals which represent a predetermined logical relationship between the data relating to the operating speed of said processor and the data relating to the operating speed of said memory as provided by said receiving and storing means.

10. A memory controlling apparatus according to claim 9, wherein said second means in said control means includes decoder means for producing timing signals in response to the output of said counter means, and third means responsive to said timing signals from said decoder means and said output control signals from said logic circuit means for producing said signal to command said memory to transmit data.

11. A memory controlling apparatus according to claim 10, wherein said counter means is connected to receive said start signal from said processor so as to be reset thereby.

12. A memory controlling apparatus according to claim 6, wherein said first means in said control means comprises logic circuit means for producing output control signals which represent a predetermined logical relationship between the data relating to the operating speed of said processor and the data relating to the operating speed of said memory as provided by said receiving and storing means.

13. A memory controlling apparatus according to claim 12, wherein said second means in said control means includes decoder means for producing timing signals in response to the output of said counter means, and third means responsive to said timing signals from said decoder, said output control signals from said logic circuit means and signals from said processor as to the type of access to said memory for producing said signal to command said memory to transmit data.

14. A memory controlling apparatus according to claim 13, wherein said counter means is connected to receive said start signal from said processor so as to be reset thereby.