Stacked semiconductor device with sloping sides

• US 4,500,905 A
• Filed: 09/28/1982
• Issued: 02/19/1985
• Est. Priority Date: 09/30/1981
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Shibata, Tadashi
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Mintel, William A.
• Application Number:
  US06/425,513
• Time in Patent Office: 875 Days
• Field of Search: 357/68, 357/40, 357/55, 357/41, 357/56, 357/76
• US Class Current: 257/74
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: H01L 21/76248 using lateral overgrowth techniques, i.e. ELO techniques
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Provided is a stacked semiconductor device wherein a plurality of semiconductor layers integrated with semiconductor elements are stacked with an insulating layer interposed between two adjacent of said semiconductor layers. This semiconductor device has one or more inclined faces extending over two or more of said semiconductor layers. These inclined faces are formed thereon with an interconnection layer or semiconductor element for effecting the transmission and reception of signals between circuits, having said semiconductor elements, formed in the different semiconductor layers, through another insulating layer.

Claims

1. A stacked semiconductor device comprising:

a plurality of semiconductor layers each having integrated circuits stacked with an insulating layer interposed between two adjacent of said semiconductor layers, and

which has at least one inclined face defined by the sloping sides of two or more of said semiconductor layers and one or more of said insulating layers interposed therebetween,

said inclined face being formed thereon through another insulating layer, with at least one element for effecting the transmission and reception of signals between said integrated circuits formed in the different semiconductor layers,

said element being one member selected from the group consisting of an interconnection layer, a semiconductor element and a controller for the respective integrated circuits of said semiconductor layers.

2. The stacked semiconductor device according to claim 1 wherein said element for effecting the transmission and reception of said signals is an interconnection layer and said interconnection layer is formed of aluminum.

3. The stacked semiconductor device according to claim 1 wherein said element of effecting the transmission and reception of said signals is an interconnection layer and said interconnection layer is formed of aluminum based alloy.