Multi-rate branch metric processor for maximum-likelihood convolutional decoder

• US 4,500,994 A
• Filed: 10/04/1982
• Issued: 02/19/1985
• Est. Priority Date: 10/04/1982
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: McCallister, Ronald D., Crawford, James J.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/432,489
• Time in Patent Office: 869 Days
• Field of Search: 371/30, 371/37, 371/43, 371/44
• US Class Current: 714/794
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors

Abstract

A branch metric processor for use in a maximum-likelihood convolutional decoder accepts a set of soft-decision symbols, an indicator of a level of quantization thereof and a set of erase control signals and generates branch metrics for base code rates of 1/3 and 1/2. The apparatus represents a substantial reduction in complexity over prior art devices. Erasure of selected symbols allows the processor to generate branch metrics for higher code rates and is advantageous in very low code rate applications.

Claims

1. In a maximum-likelihood convolutional decoder, a branch metric processor comprising:

first input means for receiving a predetermined number of symbols and an indication of a level of quantization thereof;

second input means for receiving at least one erase control signal;

calculation means coupled to said first and second input means for operating on said symbols and level of quantization, said calculation means being responsive to said at least one erase control signal to erase at least one of said symbols, said calculation means also being responsive to a select control signal to produce branch metrics corresponding to a selected one of at least two base code rates.

2. A branch metric processor according to claim 1 wherein a first stage of said calculation means comprises:

circuit means coupled to said first and second input means for producing a first set of signals and a second set of signals, each of said first and second sets of signals having a number of signals equal to said number of symbols, each of said signals in said first set being equal to a difference between said level of quantization minus one and one of said symbols, each of said signals in said second set being equal to one of said symbols, said circuit means being responsive to said at least one erase control signal to set at least one signal in said first set and at least one corresponding signal in said second set equal to zero.

3. A branch metric processor according to claim 2 wherein said calculation means further comprises:

summation means coupled to said first stage for producing a set of sums, each of said sums having a number of addends equal to said number of symbols, said set of sums including all of the possible combinations of said signals in said first and second sets but excluding redundant combinations and combinations including a signal from said first set and the corresponding signal from said second set; and

output means coupled to said summation means for outputing said set of sums, said output means being responsive to said select control signal to select one of said at least two base code rates.

4. A branch metric processor according to claim 1 further comprising:

shift means coupled between said first input means and said calculation means for adjusting said symbols responsive to said indication of said level of quantization thereof.

5. A branch metric processor according to claim 2 wherein said circuit means comprises:

a number of summing circuits equal to said number of symbols, each of said summing circuits having a non-inverted input equal to said level of quantization minus one and an inverted input equal to one of said symbols; and

at least one double-pole, double-throw switch having a first position in which a first output is equal to an output of one of said summing circuits and a second output is equal to the symbol at said inverted input of the same summing circuit and a second position in which both outputs are equal to zero, the position of each of said switches being determined by one of said at least one erase control signals.

6. In a maximum-likelihood convolutional decoder, a branch metric processor for generating branch metrics corresponding to base code rates of 1/X and 1/Y, where X>

Y, comprising;

a first set of input registers comprising X registers each adapted to receive a soft-decision symbol;

a quantization input register adapted to receive an indication of a level of quantization of said symbols;

a second set of input registers comprising X registers each adapted to receive an erase control signal, each of said registers in said second set being associated with a register in said first set;

means coupled to said quantization input register for producing a signal N equal to said level of quantization minus one;

a set of X subtraction circuits each coupled to one of said first set of input registers and to said signal N to produce a signal equal to N minus said symbol received by said one of said input registers;

a set of X switches having first and second outputs, each of said switches having a first position in which said first output is coupled to one of said subtraction circuits and said second output is coupled to the input register coupled to said one of said subtraction circuits and a second position in which each of said first and second outputs is equal to zero, each of said switches being coupled to said input register in said second set which is associated with the input register coupled to said one of said subtraction circuits, whereby the erase control signal received by said input register determines the position of the switch;

summation means coupled to said outputs of said switches for producing a set of sums, each of said sums having a number of addends equal to X, said set of sums including all possible combinations of said outputs but excluding redundant combinations and combinations including two outputs from any one of said switches; and

output means coupled to said summation means for outputing said sums as branch metrics, said output means being responsive to a select control signal to select the proper of said sums to correspond to one of said base code rates.

7. A branch metric processor according to claim 6 further comprising:

shift means coupled between said first set of input registers and said subtraction circuits for adjusting said received symbols in response to said indication of said level of quantization thereof.

8. In a maximum-likelihood convolutional decoder a method of branch metric processing comprising the steps of:

receiving a set of soft-decision symbols and an indication of a level of quantization thereof;

receiving at least one erase control signal;

producing a first set of signals each of which is equal to said level of quantization minus one minus one of said symbols;

producing a second set of signals each of which is equal to one of said symbols;

responding to said at least one erase control signal by setting an indicated signal in said first set and a corresponding signal in said second set equal to zero;

producing a set of sums each of which has a number of addends equal to a number of said received symbols, said set including all possible combinations of signals from said first and second sets, but excluding redundant combinations and combinations including a signal from said first set and the corresponding signal from said second set; and

receiving and responding to a base rate select signal by outputting said sums as branch metrics for a selected one of at least two base code rates.