Offset QPSK demodulator and receiver

• US 4,501,002 A
• Filed: 02/28/1983
• Issued: 02/19/1985
• Est. Priority Date: 02/28/1983
• Status: Expired due to Term

• Current Assignee: Richard C. Auchterlonie
• Original Assignee: Richard C. Auchterlonie
• Inventors: Auchterlonie, Richard C.
• Primary Examiner(s): Ng, Jin F.
• Application Number:
  US06/470,053
• Time in Patent Office: 722 Days
• Field of Search: 375/53, 375/86, 375/111, 375/118.81, 375/77, 375/52, 375/54, 375/83, 329/50, 329/122, 329/124
• US Class Current: 375/332
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop

Abstract

An offset QPSK demodulator samples inphase and quadraphase channels at the data rate and derives carrier phase and clock phase control signals even if the samples are hard limited. The demodulator may be fabricated as a low cost integrated circuit. In one embodiment, a data clock having a 50% duty cycle clocks D flip-flops to store inphase data samples and quadraphase control samples upon rising clock transitions, and to store inphase control samples and quadraphase data samples upon falling clock transitions. To generate a tristate carrier phase control signal, an inphase exclusive-OR gate compares the inphase control samples to the complement of the quadraphase data samples, and a quadraphase exclusive-OR gate compares the quadraphase control samples to the inphase data samples. To generate a tristate clock phase control signal, an inphase exclusive-OR gate compares the inphase control samples to the inphase data samples, and a quadraphase exclusive-OR gate compares the quadraphase control samples to the quadraphase data samples. Transition-detecting D flip-flops and exclusive-OR gates enable the outputs of the respective control signal-generating exclusive-OR gates to assert active tristate signals for one-half data bit periods only when there is a transition in the data samples of the respective channel. The transition-indicating signals are logically ORed to provide differentially decoded data.

Claims

1. An offset QPSK receiver for receiving an offset QPSK signal including data at a predetermined data rate modulated on a suppressed carrier wherein the offset QPSK signal is approximately the sum of a transmitted inphase data stream multiplied by a first suppressed modulating singal at approximately the frequency of the suppressed carrier plus a transmitted quadraphase data stream mutiplied by a second suppressed modulating signal at approximately the frequency of the suppressed carrier and approximately in phase quadrature with said first suppressed modulating signal, the transmitted inphase data stream having a substantial proportion of data transitions offset from the data transitions in the transmitted quadraphase data stream, said offset QPSK receiver comprising, in combination,

(a) means for effectively multiplying the offset QPSK signal by a locally-generated first modulating signal at approximately the frequency of the suppressed carrier and a locally-generated second modulating signal at approximately the frequency of the suppressed carrier and approximately in phase quadrature with said locally-generated first modulating signal, the phase of said locally-generated modulating signals relative to the phase of the suppressed modulating signals being responsive to a carrier phase control signal, to thereby generate respective inphase and quadraphase signals from said offset QPSK signal responsive to said carrier phase control signal,

(b) respective means for generating hard limited inphase and quadraphase signals from said inphase and quadraphase signals,

(c) a data clock for generating a periodic data clocking signal in response to a data phase control signal, and

(d) digital circuit means responsive to said respective hard limited inphase and quadraphase signals and said data clocking signal for

(1) obtaining respective received inphase and quadraphase data streams,

(2) generating said data phase control signal so that said received data streams become substantially phase synchronized to said transmitted data streams, and

(3) generating said carrier phase control signal so that said locally-generated modulating signals become substantially phase synchronized to said suppressed modulating signals and so that said carrier phase control signal is unresponsive to the amplitudes of the inphase and quadraphase signals and thereby unresponsive to the amplitude of the offset QPSK signal.

2. The offset QPSK receiver as claimed in claim 1, wherein said digital circuit means includes means for sampling the hard limited inphase and quadraphase signals substantially simultaneously and approximately at the data rate, and means for generating the carrier phase control signal from the samples of the hard limited inphase and quadraphase signals.

3. An offset QPSK receiver for receiving an offset QPSK signal including data at a predetermined data rate modulated on a suppressed carrier wherein the offset QPSK signal is approximately the sum of a transmitted inphase data stream multiplied by a first suppressed modulating singal at approximately the frequency of the suppressed carrier plus a transmitted quadraphase data stream multiplied by a second suppressed modulating signal at approximately the frequency of the suppressed carrier and approximately in phase quadrature with said first suppressed modulating signal, the transmitted inphase data stream having a substantial proportion of data transitions offset from the data transitions in the transmitted quadraphase data stream, said offset QPSK receiver comprising, in combination,

(a) means for effectively multiplying the offset QPSK signal by a locally-generated first modulating signal at approximately the frequency of the suppressed carrier and a locally-generated second modulating signal at approximately the frequency of the suppressed carrier and approximately in phase quadrature with said locally-generated first modulating signal, the phase of said locally-generated modulating signals relative to the phase of the suppressed modulating signals being responsive to a carrier phase control signal, to thereby generate respective inphase and quadraphase signals from said offset QPSK signal responsive to said carrier phase control signal,

(b) respective means for generating hard limited inphase and quadraphase signals from said inphase and quadraphase signals,

(c) a data clock for generating a periodic data clocking signal in response to a data phase control signal, and

(d) circuit means responsive to said respective hard limited inphase and quadraphase signals and said data clocking signal for

(1) obtaining respective received inphase and quadraphase data streams,

(2) generating said data phase control signal so that said received data streams become substantially phase synchronized to said transmitted data streams, and

(3) generating said carrier phase control signal so that said locally-generated modulating signals become substantially phase synchronized to said suppressed modulating signals,

wherein the carrier phase control signal is a tristate signal active upon the occurrence of transitions in the inphase data stream and upon transitions in the quadraphase data stream.

4. A PSK receiver for receiving a PSK signal including data at a predetermined data rate modulated on a suppressed carrier, said PSK receiver comprising, in combination,

(a) means for effectively multiplying the PSK signal by a locally-generated first modulating signal at approximately the frequency of the suppressed carrier and a locally-generated second modulating signal at approximately the frequency of the suppressed carrier and approximately in phase quadrature with said locally-generated first modulating signal, the phase of said locally-generated modulating signals relative to the phase of the suppressed carrier being responsive to a carrier phase control signal, to thereby generate respective inphase and quadraphase signals from said PSK signal responsive to said carrier phase control signal,

(b) respective means for generating hard limited inphase and quadraphase signals from said inphase and quadraphase signals,

(c) a data clock for generating a periodic data clocking signal in response to a data phase control signal, and

(d) circuit means responsive to said respective hard limited inphase and quadraphase signals and said data clocking signal for

(1) obtaining a received data stream corresponding to said data modulated on said suppressed carrier,

(2) generating said data phase control signal so that said received data stream becomes substantially phase synchronized to said transmitted data stream, and

(3) generating said carrier phase control signal so that said locally-generated modulating signals become substantially phase synchronized to said suppressed carrier,

wherein the means for effectively multiplying the PSK signal comprise a transformer having a primary coil excited by the PSK signal, a center-tapped secondary coil having the center tap substantially at signal ground, and a ring of four switching elements bridging the secondary coil of the transformer, the switching elements being individually and sequentially enabled at approximately the suppressed carrier frequency, the ring of switching elements thereby providing inphase and quadraphase balanced modulator outputs.

5. The PSK receiver as claimed in claim 4, further comprising DC blocking capacitors in the inphase and quadraphase channels between the balanced modulator outputs and the respective hard limited signal outputs.

6. The PSK receiver as claimed in claim 4, further comprising a four-state binary decoder providing the four signals for sequentially enabling the switching elements, a pseudorandom binary sequence generator, and an exclusive-OR gate for modulating the most significant bit input to the binary decoder by the pseudorandom binary sequence.

7. The PSK receiver as claimed in claim 4, wherein said circuit means includes a microcomputer programmed to provide means for receiving the hard limited inphase and quadraphase signals and outputting the carrier phase control signal.

8. In an offset QPSK demodulator having a local oscillator generating two outputs in phase quadrature, means for multiplying the offset QPSK signal by the two oscillator outputs and low pass filters for generating inphase and quadraphase signals from the outputs of the means for multiplying, and a data clock periodically defining sampling times at approximately the data rate of the QPSK signal, a method for generating a carrier phase control signal for adjusting the local oscillator phase to acquire the phase of the suppressed carrier in the offset QPSK signal, the method comprising the steps of:

(a) periodically sampling both the inphase signal and the quadraphase signal at approximately the sampling times defined by the data clock,

(b) alternately designating the samples in the inphase channel as inphase data samples and inphase control samples, and designating the samples in the quadraphase channel coincident with the inphase data samples as quadraphase control samples, and designating the samples in the quadraphase channel coincident with the inphase control samples as quadraphase data samples, the inphase and quadraphase data samples being hard limited, and

(c) generating the carrier phase control signal to change the phase of the local oscillator if a given data sample in a given one of the channels differs in logic state from the data sample in the given channel immediately preceding the given data sample, by generating the carrier phase control signal from the control sample in the channel immediately preceding the given data sample by conditionally reversing the polarity of the control sample in response to the logic state of the data sample in the channel other than the given channel sampled coincident with the control sample in the given channel, wherein the reversing occurs when the data sample in the other channel is in a first binary logic state if the other channel is the inphase channel, and in the second binary logic state opposite to the first when the other channel is the quadraphase channel.

9. The method as claimed in claim 8, wherein the control samples are hard limited.

10. The method as claimed in claim 8, further comprising the step of changing the phase of the data clock in response to a clock phase control signal if a given data sample in a given one of the channels differs in logic state from the data sample in the given channel immediately preceding the given data sample, by generating the clock phase control signal from the control sample in the given channel immediately preceding the given data sample by conditionally reversing the polarity of the control sample in response to the polarity of the transition between the given data sample and the data sample in the given channel immediately preceding the given data sample.

11. The method as claimed in claim 10, wherein the control samples are hard limited.

12. In an offset QPSK demodulator receiving inphase and quadraphase signals in respective inphase and quadraphase channels and demodulating the signals to obtain data at a predetermined data rate, said inphase and quadraphase signals encoding respective inphase and quadraphase data streams having data transitions substantially offset from each other, a phase control signal generating apparatus comprising, in combination,

(a) means for sampling the inphase and quadraphase signals at approximately the data rate to alternately obtain data samples and control samples for each channel,

(b) means responsive to the data samples in each channel for generating transition-indicating signals for each channel, and

(c) first tristate means for comparing the data samples from each channel with the control samples from the other channel to generate a carrier phase control signal, said first tristate means being active in response to the transition-indicating signals.

13. The combination as claimed in claim 12, further comprising second tristate means for comparing the control samples from each channel with the data samples from the same channel to generate a data clock phase control signal, said second tristate means for comparing being active in response to the transition-indicating signals.

14. The combination as claimed in claim 13, wherein the second tristate means comprise an exclusive-OR gate for each channel receiving the control samples of the respective channel and the data samples of the respective channel, and tristate gating means for each channel receiving the output of the exclusive-OR gate for the channel and being enabled by the transition-indicating signal for the channel.

15. The combination as claimed in claim 13 wherein the means for sampling comprise a data clock having approximately a 50% duty cycle output cycling at approximately half the data rate, two D flip-flops clocked upon the rising transitions of the clock, one receiving the inphase signal and the other receiving the quadraphase signal, and two D flip-flops clocked upon the falling transitions of the clock output, one receiving the inphase signal and the other receiving the quadraphase signal.

16. The phase control signal generating apparatus as claimed in claim 15, wherein the means for generating the transition-indicating signal comprise, for each channel, a delaying D flip-flop and a first exclusive-OR gate comparing the input of the D flip-flop to the output of the D flip-flop, the flip-flop receiving a data sample, and the flip-flop being clocked by a clock transition polarity selected so that the transition-indicating signal from the exclusive-OR gate is active at most for half clock cycles.

17. The phase control signal apparatus as claimed in claim 12, wherein the means for sampling comprises a data clock having a 50% duty cycle output cycling at approximately half the data rate signal, two D flip-flops clocked upon the rising transitions of the clock output, one receiving the inphase signal and the other receiving the quadraphase signal, and two D flip-flops clocked upon falling transitions of the clock output, one receiving the inphase signal and the other receiving the quadraphase channel signal.

18. The phase control signal generating apparatus as claimed in claim 17, wherein the means for generating the transition-indicating signal comprise, for each channel, a delaying D flip-flop and a first exclusive-OR gate comparing the input of the D flip-flop to the output of the D flip-flop, the flip-flop receiving a data sample, and the flip-flop being clocked by a clock transition polarity selected so that the transition-indicating signal from the exclusive-OR gate is active at most for half clock cycles.

19. The combination as claimed in claim 12, wherein the first tristate means comprise an exclusive-OR gate for each channel receiving the control samples of the respective channel and data samples of the other channel, and tristate gating means for each channel for receiving the output of the exclusive OR gate for the respective channel and being enabled by the transition-indicating signal of the respective channel.

20. The combination as claimed in claim 12, further comprising means for combining the transition-indicating signals for the channels to generate a differentially decoded data stream.