Method for fabricating overlaid device in stacked CMOS
First Claim
1. A method for fabricating a stacked CMOS device, comprising the steps of;
- providing a substrate;
growing a gate oxide on said substrate;
forming a gate electrode in desired gate locations, said gate electrode being formed to have substantially vertically sidewalls in desired gate locations;
depositing and anistropically etching a dopant source material, to provide sidewall filaments of said dopant source adjacent to said sidewalls of said gate electrode;
depositing a thin polysilicon layer over all, said thin polysilicon layer being insulated from said gate electrode and comprising a second-type dopant;
providing a mask over said gate electrode, said mask being wider than the width of said gate electrode, and implanting a heavy concentration of a second-conductivity type dopant into said thin polysilicon layer;
whereby said gate electrode addresses both a field effect transistor having first-type sources and drains in said substrate, and a field effect transistor having second-type sources and drains and a polysilicon channel.
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Abstract
In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlaid p-channel device. The p-channel polysilicon device has its channel self-aligned to the gate, by the use of a boron-doped oxide at the sidewalls of the gate. This boron-doped oxide provides a dopant source which dopes the second polysilicon layer to provide heavily doped source/drain extension regions which are self-aligned to the gate in first poly. A mask level is still required to pattern the sources and drains, but the self-aligned source/drain extension regions mean that the source/drain mask level can have a reasonable alignment tolerance.
39 Citations
5 Claims
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1. A method for fabricating a stacked CMOS device, comprising the steps of;
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providing a substrate; growing a gate oxide on said substrate; forming a gate electrode in desired gate locations, said gate electrode being formed to have substantially vertically sidewalls in desired gate locations; depositing and anistropically etching a dopant source material, to provide sidewall filaments of said dopant source adjacent to said sidewalls of said gate electrode; depositing a thin polysilicon layer over all, said thin polysilicon layer being insulated from said gate electrode and comprising a second-type dopant; providing a mask over said gate electrode, said mask being wider than the width of said gate electrode, and implanting a heavy concentration of a second-conductivity type dopant into said thin polysilicon layer; whereby said gate electrode addresses both a field effect transistor having first-type sources and drains in said substrate, and a field effect transistor having second-type sources and drains and a polysilicon channel. - View Dependent Claims (2, 3, 5)
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4. The method of claim 10, further comprising the step of:
patterning said thin polysilicon layer to achieve a desired device configuration.
Specification