Method and apparatus for digital data compression

• US 4,503,510 A
• Filed: 12/05/1983
• Issued: 03/05/1985
• Est. Priority Date: 10/31/1980
• Status: Expired due to Fees

• Current Assignee: SRI International, Inc.
• Original Assignee: SRI International, Inc.
• Inventors: Weaver, Charles S.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/557,968
• Time in Patent Office: 456 Days
• Field of Search: 364/715, 364/724, 364/900, 343/17.2 PC, 358/133, 358/135, 370/7
• US Class Current: 708/203
• CPC Class Codes: H03M 7/42 using table look-up for the coding or decoding process, e.g. using read-only memory H03M7/4006 takes precedence

Abstract

Digital data compression method and means are disclosed which allow for transmission of digital data over a short time period and/or narrow bandwidth transmission line. Also a maximum amount of information may be stored on a movable recording medium using data compression method of this invention. Digital signals to be stored and/or transmitted first are compressed using a finite-impulse response digital compression filter which generates estimated signal values which are subtracted from actual signal values to provide a sequence of difference signals. The difference signals are encoded using a truncated Huffman type encoding method and means, and the encoded signals are transmitted to a remote receiver and/or are recorded. The receiver includes a decoder and digital reconstruction filter for exact reproduction of transmitted digital signals. The invention is well adapted for storage and/or transmission of three lead electrocardiogram (ECG) signals, recording and playback of music, and the like.

Claims

1. Digital compression filter means for producing a stream of compressed digital signals, Δ

_n, from an input stream of digital sample signals, f_n, comprising,

delay means having an input to which said input stream is supplied, said delay means including a plurality of sample signal length sections,

multiplexer means to which digital sample signal outputs from sections of the delay means are supplied, and

an arithmetic and logic unit responsive to digital sample signals from said multiplexer means, said arithmetic and logic unit having an output stream of compressed digital signals in accordance with the following equation

space="preserve" listing-type="equation">Δ

.sub.n =y.sub.n -y.sub.n-1 +2.sup.-m.sbsp.2 y.sub.n-1

wherein;

space="preserve" listing-type="equation">y.sub.n =0.5f.sub.n -0.5f.sub.n-1 +2.sup.-m.sbsp.1-1 f.sub.n-1,

m₁ and m₂ are positive integers, and

n is an integer comprising the argument, or index, of the function.

2. Digital compression filter means as defined in claim 1 wherein m₁ and m₂ are integers between 2 and 6.

3. Digital compression filter means as defined in claim 2 wherein m₁ and m₂ are equal.

4. Digital compression filter means for producing a stream of compressed digital signals, Δ

_n, from an input stream of digital sample signals, f_n, comprising,

delay means having an input to which said input stream of digital sample signals, f_n, is supplied, said delay means including a plurality of sections each of which is the length of a sample signal,

multiplexer means to which digital sample signal outputs from sections of the delay means are supplied, and

an arithmetic and logic unit responsive to digital sample signals from said multiplexer means, said arithmetic and logic unit having an output stream of compressed digital signals in accordance with the following equation ##EQU10## wherein m₁ and m₂ are positive integers, and

n is an integer comprising the argument, or index, of the function.

5. Digital compression filter means as defined in claim 4 wherein m₁ and m₂ are integers between 2 and 6.

6. Digital compression filter means as defined in claim 5 wherein m₁ and m₂ are equal.

7. Digital decompression filter means for producing a stream of equal-length digital signals, f_n+1, from a stream of equal-length compressed digital signals, Δ

_n, produced in accordance with the following equation

space="preserve" listing-type="equation">Δ

.sub.n =0.5f.sub.n+1 -f.sub.n +0.5f.sub.n-1

wherein n is an integer comprising the argument, or index, of the function,

said digital decompression filter means comprising

an arithmetic and logic unit for performing addition, subtraction, and multiplication by shifting operations,

delay means having an input to which the output from the arithmetic and logic unit is supplied, said delay means including a plurality of sections each of which is the length of the equal-length decompressed digital signals,

multiplexer means for connecting the stream of equal length compressed digital signals, Δ

_n, and outputs from sections of the delay means to the input of the arithmetic and logic unit,

said arithmetic and logic unit having an output stream of digital signals in accordance with the following equation

space="preserve" listing-type="equation">f.sub.n+1 =(f.sub.n -Δ

.sub.n)/0.5 -f.sub.n-1

8. Digital decompression filter means for producing a stream of equal-length digital signals, f_n, from a stream of equal-length compressed digital signals, Δ

_n, produced in accordance with the following equation

space="preserve" listing-type="equation">Δ

.sub.n =y.sub.n -y.sub.n-1 +2.sup.-m.sbsp.2 y.sub.n-1

wherein

space="preserve" listing-type="equation">y.sub.n =0.5f.sub.n -0.5f.sub.n-1 +2.sup.-m.sbsp.1.sup.-1 f.sub.n-1,

m₁ and m₂ are positive integers, and

n is an integer comprising the argument, or index, of the function,

said digital decompression filter means comprising

an arithmetic and logic unit for performing addition, subtraction, and multiplication by shifting operations,

first delay means having an input and including a plurality of sections each of which is the length of the equal-length decompressed digital signals, f_n,

second delay means having an input and including a single section with a length equal to that of the equal-length decompressed digital signals, f_n,

demultiplexer means for connecting outputs from the arithmetic and logic unit to said first and second delay means,

multiplexer means for connecting outputs from the plurality of sections of the first delay means, the output from the second delay means, and the stream of equal length compressed digital signals, Δ

n, to the input of the arithmetic and logic unit,

said arithmetic and logic unit having an output stream of digital signals which includes signals produced in accordance with the following equations

space="preserve" listing-type="equation">f.sub.n =y.sub.n +f.sub.n-1 -2.sup.-m.sbsp.2 f.sub.n-1,

and

space="preserve" listing-type="equation">y.sub.n =2Δ

.sub.n +y.sub.n-1 -2.sup.m.sbsp.1 y.sub.n-1

wherein m₁ and m₂ are the same positive integers employed in the production of said digital difference signals, Δ

_n,

said y_n signals being supplied to the input of said first delay means through said demultiplexer means, and

said f_n signals being supplied to the input of said second delay means through said demultiplexer means.

9. Digital decompression filter means as defined in claim 8 wherein m₁ and m₂ are integers between 2 and 6.

10. Digital decompression filter means as defined in claim 9 wherein m₁ and m₂ are equal.