Common circuit for dynamic memory refresh and system clock function
DCFirst Claim
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1. A circuit for refreshing a dynamic memory comprising:
- a multi-stage binary counter for providing output bits corresponding to memory addresses and a cumulation count equivalent to the elapsed pulses of a systems clock, andrefresh message generating means operatively coupling said binary counter to said dynamic memory for generating a refresh message, said refresh message generating means including addressing means for addressing said memory at an address specified by said output bits such that said refresh meassage is applied at said address so as to refresh said memory.
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Abstract
A time-of-day counter having a plurality of register stages for counting system clock pulses and for providing signals indicative of the status of each of the register stages is coupled by a bus to a dynamic memory of the type requiring a refresh cycle. Logic means operatively coupled to the time-of-day counter operate to pass the signals present at the output of the time-of-day registers onto the bus as memory address signals so as to effectively utilize the output signals of the time-of-day counter to periodically address all portions of the memory and to provide a refresh signal as each portion of the memory is addressed.
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Citations
10 Claims
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1. A circuit for refreshing a dynamic memory comprising:
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a multi-stage binary counter for providing output bits corresponding to memory addresses and a cumulation count equivalent to the elapsed pulses of a systems clock, and refresh message generating means operatively coupling said binary counter to said dynamic memory for generating a refresh message, said refresh message generating means including addressing means for addressing said memory at an address specified by said output bits such that said refresh meassage is applied at said address so as to refresh said memory. - View Dependent Claims (2, 3, 4)
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5. A circuit for refreshing a memory, said memory having a plurality of memory portions each comprised of a multiplicity of memory elements arranged in rows and columns, said memory particularly adapted for use in a computing system having a bus and a source of timing pulses, said circuit comprising:
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a timing pulse counter for counting timing pulses from said source of timing pulses and providing output signals corresponding to the number of pulses counted; said timing pulse counter being connected to said bus for transmitting said output signals to said memory; first logic means coupled to said counter for providing a bus request signal usable by said computing system for controlling access to said bus for the transmission of said output signals to said memory; second logic means for providing a memory enabling signal to said memory for enabling said memory upon the granting of said bus access, and having gate means for gating select ones of the output signals of said timing pulse counter onto said bus as memory addresses; and decoder means coupled to said bus for receiving said gated output signals and directing a refresh enable signal to the memory portion addressed by said gated output signals. - View Dependent Claims (6, 7, 8, 9, 10)
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Specification