Common circuit for dynamic memory refresh and system clock function

• US 4,503,525 A
• Filed: 04/07/1982
• Issued: 03/05/1985
• Est. Priority Date: 04/07/1982
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Malik, Ashgar K., Celio, John A.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/366,275
• Time in Patent Office: 1,063 Days
• Field of Search: 365/222, 365/228
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A time-of-day counter having a plurality of register stages for counting system clock pulses and for providing signals indicative of the status of each of the register stages is coupled by a bus to a dynamic memory of the type requiring a refresh cycle. Logic means operatively coupled to the time-of-day counter operate to pass the signals present at the output of the time-of-day registers onto the bus as memory address signals so as to effectively utilize the output signals of the time-of-day counter to periodically address all portions of the memory and to provide a refresh signal as each portion of the memory is addressed.

Claims

1. A circuit for refreshing a dynamic memory comprising:

a multi-stage binary counter for providing output bits corresponding to memory addresses and a cumulation count equivalent to the elapsed pulses of a systems clock, and

refresh message generating means operatively coupling said binary counter to said dynamic memory for generating a refresh message, said refresh message generating means including addressing means for addressing said memory at an address specified by said output bits such that said refresh meassage is applied at said address so as to refresh said memory.

2. The circuit according to claim 1 wherein said refresh message generating means is comprised in part of:

first logic means responsive to said output bits for enabling said refresh message generating means thereby timing said refresh message for said memory.

3. The circuit according to claim 2 wherein said refresh message generating means is further comprised of:

second logic means for providing an enabling signal to said memory usable by said memory for enabling said memory to receive said refresh message, and said addressing means includes means for establishing selected ones of said output bits as memory addresses.

4. The circuit according to claim 2 wherein said addressing means further comprises:

decoder means for decoding selected ones of said output bits as a function of the output bits for use as memory addresses.

5. A circuit for refreshing a memory, said memory having a plurality of memory portions each comprised of a multiplicity of memory elements arranged in rows and columns, said memory particularly adapted for use in a computing system having a bus and a source of timing pulses, said circuit comprising:

a timing pulse counter for counting timing pulses from said source of timing pulses and providing output signals corresponding to the number of pulses counted;

said timing pulse counter being connected to said bus for transmitting said output signals to said memory;

first logic means coupled to said counter for providing a bus request signal usable by said computing system for controlling access to said bus for the transmission of said output signals to said memory;

second logic means for providing a memory enabling signal to said memory for enabling said memory upon the granting of said bus access, and having gate means for gating select ones of the output signals of said timing pulse counter onto said bus as memory addresses; and

decoder means coupled to said bus for receiving said gated output signals and directing a refresh enable signal to the memory portion addressed by said gated output signals.

6. The circuit according to claim 5 wherein said timing pulse counter includes a shift register having a plurality of stages, each stage for containing a binary bit of the value representative of the counted timing pulses;

and

wherein said first logic means is comprised of;

a first AND gate receiving as inputs the binary bits from the first two stages of said shift register and the timing pulses; and

a second AND gate receiving as inputs the output from said first AND gate and a signal indicating the busy status of said bus to provide at its output said bus request signal.

7. The circuit according to claim 5 wherein said second logic means is a one cycle shifter comprised of:

a flip-flop for receiving at one input said bus request signal and providing at its output a flip-flop output signal responsive to said bus request signal; and

gating means coupled to the output of said flip-flop for gating said flip-flop output signal to said bus after a desired delay.

8. The circuit according to claim 7 wherein said timing pulse counter includes a 32-bit register for providing binary signals having a plurality of bits numbered from 1 through 32, said binary signals corresponding to the time-of-day and wherein bits numbered from 3 through 10 are further used as a portion of said memory address indicative of the memory row address, bits numbered from 11 through 18 are used as a portion of said memory address indicative of the memory column address, bits numbered from 19 through 24 are used as a memory portion select signal and bit numbered 29 is used as said refresh enable signal.

9. The circuit according to claim 8 and further comprising:

a multiplexer coupled to said bus and to said memory for alternately providing said row address and said column address to said memory.

10. The circuit according to claim 9 wherein said decoder is coupled to said bus and to said memory for applying said refresh enable signal to the memory portion indicated by said row and column addresses.