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Common circuit for dynamic memory refresh and system clock function

DC
  • US 4,503,525 A
  • Filed: 04/07/1982
  • Issued: 03/05/1985
  • Est. Priority Date: 04/07/1982
  • Status: Expired due to Term
First Claim
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1. A circuit for refreshing a dynamic memory comprising:

  • a multi-stage binary counter for providing output bits corresponding to memory addresses and a cumulation count equivalent to the elapsed pulses of a systems clock, andrefresh message generating means operatively coupling said binary counter to said dynamic memory for generating a refresh message, said refresh message generating means including addressing means for addressing said memory at an address specified by said output bits such that said refresh meassage is applied at said address so as to refresh said memory.

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