Parallel path self-testing system

• US 4,503,537 A
• Filed: 11/08/1982
• Issued: 03/05/1985
• Est. Priority Date: 11/08/1982
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McAnney, William H.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Fleming, Michael R.
• Application Number:
  US06/440,065
• Time in Patent Office: 848 Days
• Field of Search: 364/900, 364/200, 371/25, 371/38, 371/16, 371/15, 371/20, 324/73 R, 324/73 AT
• US Class Current: 714/728
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The LSSD scan paths of each logic circuit chip on a circuit module are connected to additional test circuit chips on the same module. The test chips contain a random signal generator and data compression circuit to perform random stimuli signature generators and also contain switching circuits to connect the scan paths of the chips in parallel between different stages of the random signal generator and the data compression means for random stimuli signature generators and to disconnect the scan paths from the signal generator and data compression circuitry and arrange them serially in a single scan path to perform other tests.

Claims

1. In a combinational and sequential logic circuit arranged on a plurality of logic units with memory circuits on each logic unit coupled together to form a shift register which shift register can be enabled to provide a shift register scan path for testing the logic circuit and disabled while the logic circuit is performing its designed logic function, apparatus for performing self-testing of the logic circuit using a multistage generator means to generate testing sequences for the self-testing and a multistage data compression means to compress the response of the logic circuits the improvement comprising:

test circuit unit means containing the multistage random signal generator means for the generation of testing sequences and the multistage data compression means for the compression of the logic signals,

circuit means coupling the scan paths of said logic units to said test circuit unit means and,

logic means for coupling said shift register scan paths of said logic units in a plurality of parallel shift register paths between different stages of said signal generator means and said multistage data compression means for supplying said testing sequences to said memory circuits in said plurality of parallel paths so the response of said logic circuits is transmitted along said plurality of parallel paths to be compressed by said multistage data compression means for developing a self-test signature.

2. The combination of claim 1 wherein said logic means includes means for connecting said parallel shift register paths into a single shift register scan path including the shift register paths of all the individual logic units.

3. The combination of claim 2 wherein the stages of said multistage random signal generator and said multistage data compression means and said memory circuits are all operated to shift data between them using the same set of shift pulses.