Method and system to recognize change in the storage characteristics of a programmable memory

• US 4,503,538 A
• Filed: 06/21/1982
• Issued: 03/05/1985
• Est. Priority Date: 09/04/1981
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Fritz, Eberhard
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Ungerman, Mark
• Application Number:
  US06/390,291
• Time in Patent Office: 988 Days
• Field of Search: 371/20, 371/21, 371/25, 371/28, 364/200, 364/900, 365/200, 365/201, 324/73 R
• US Class Current: 714/745
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

To recognize change in the storage characteristics of programmable memory elements, particularly EPROMs, the memory content of an addressed memory element or cell is read out, the first time, at normal design voltage level; the data so read are then again read out at a changed voltage level, for example at a higher or lower read-out voltage, or higher or lower operating voltage of the EPROM, and compared. If the data do not match, the particular memory cell will have the tendency to become defective due to loss or accumulation of charge carriers in due course although, for some time yet, the specific memory cell will function satisfactorily. Detection of errors upon operation under changed voltage conditions provides early warning of failure of a cell.

Claims

1. Method to recognize change in the storage characteristics and affecting a stored memory content in a read-only memory (ROM) element, especially an erasable programmable read-only memory element (EPROM) having programmed memory cells,

in which a computer (1) is provided, capable of sequentially generating read-out command signals and the memory element or cells thereof are addressable by the computer, comprising the steps of

reading-out a first time the memory content of addressed cells of the read-only memory element with a standard or design read-out voltage;

storing the memory content of the cells of the read-only memory element, as read out the first time, in a computer memory;

reading-out a second time the memory content of said previously addressed cells of the read-only memory with a read-out voltage which differs from said standard or design read-out voltage;

comparing the content stored in the computer memory, as read out the first time, with the data derived from the cells of the memory element as read-out said second time;

and generating an error signal upon non-concurrence of the data derived from the read-only memory element as read out the second time with the content of the computer memory.

2. Method according to claim 1 wherein said step of reading-out a second time the memory content of said previously addressed cells of the read-only memory comprises the step of:

increasing the read-out voltage applied to said previously addressed cells.

3. Method according to claim 1 wherein said step of reading-out a second time the memory content of said previously addressed cells of the read-only memory comprises the step of:

decreasing the read-out voltage applied to said previously addressed cells.

4. Method according to claim 1 wherein said step of reading-out a second time the memory content of said previously addressed cells of the read-only memory comprises the step of:

changing the read-out voltage in a first direction;

changing the read-out voltage in an opposite direction, and reading out the memory content of said previously addressed cells of the read-only memory a third time;

and comparing the memory content stored in the computer memory, as read out the first time, with the data derived from the cells of the memory element as read out both the second time and as read out the third time;

and the step of generating the error signal comprises generating the error signal upon non-concurrence of the data derived from the read-only memory element with the content of the computer memory as read out either the second time or the third time.

5. Method according to claim 1 wherein the step of reading-out a second time the memory content of said previously addressed cells of the read-only memory comprises changing the read-out voltage during said second time reading-out with respect to the standard or design read-out voltage;

and further including the step of controlling the change of the read-out voltage by the computer (1).

6. Method according to claim 1, wherein the step of generating the error signal comprises providing a warning signal if the comparison step indicates disconformity in the data read out the first time and a subsequent time.

7. Method according to claim 1, wherein said computer operates in accordance with a predetermined program;

and the computer further includes a subroutine or subprogram controlling said reading-out step the first time, changing of the read-out voltage, reading out the read-only memory element content a second time and said comparison step is carried out during a pause or program gap of the computer program.

8. In combination with a read-only memory (ROM), especially an erasable programmable read-only memory (EPROM),

an incipient error recognition sytem to recognize change in the storage characteristics of memory cells in the read-only memory (ROM) element (4) having

a voltage applying means to apply operating voltage to the memory element;

a computer (1) capable of sequentially generating read-out or interrogating signals, connected to said read-only memory element, and addressing selected addressable cells in the read-only memory,

said computer having a computer having a computer memory, comprising

means (8-13) coupled to the read-only memory for controlling an operating voltage applied to the read-only memory by the voltage applying means between at least two selected voltage levels, in which one of the voltage levels is at a standard or design level, and another voltage level is changed with respect to said standard or design level in increasing or decreasing direction;

and means (5) coupled to the voltage applying means connected to and controlled by the computer (1) for reading-out the memory of said read-only memory at

(a) the standard or design voltage; and

, also

(b) at another voltage level;

the computer memory being connected for storing the content of the read-only memory during read-out of the content at said standard or design level;

said computer further including a comparator, the comparator being connected to and controlled by said selective voltage applying means (5) and connected to compare the stored memory content in the computer memory with the content of the read-only memory (ROM) being read out at said other voltage level,

wherein said computer (1) provides sequentially generated read-out command signals, and the memory element, or cells thereof are addressable by the computer;

said computer controlling

reading-out a first time the memory content of addressed cells of the read-only memory element with a standard or design read-out voltage;

storing the memory content of the cells of the read-only memory element, as read out the first time, in a computer memory;

reading-out a second time the memory content of said previously addressed cells of the read-only memory with a read-out voltage which differes from said standard or design read-out voltage;

comparing the content stored in the computer memory, as read out the first time, with the data derived from the cells of the memory element as read-out said second time;

and generating an error signal upon non-concurrence of the data derived from the read-only memory element as read out the second time with the content of the computer memory.

9. System according to claim 8, wherein said operating voltage controlling means includes a threshold circuit (8-13) having a controllable, variable threshold voltage.

10. System according to claim 8, further including a voltage stabilized power supply unit (16) connected to the memory elements (4), said power supply unit having a reference voltage terminal (7);

and wherein said means for controlling the predetermined or changed voltage level of the operating voltage for the read-only memory comprises means (8-13) for changing the reference voltage level connected to said reference voltage terminal.

11. System according to claim 8, further comprising means (5) connected to and controlled by the computer (1) for controlling the voltage level of the operating voltage applied to said read-only memory element.

12. System according to claim 8, wherein said computer (1) includes comparator means for comparing

(a) data read-out from an addressed memory cell when the memory cell is supplied with operating voltage at said predetermined standard or design level voltage

with

(b) the data read-out when said memory cell is supplied with operating voltage at a voltage level which is changed with respect to said predetermined standard or design level.

13. System according to claim 12, further including warning signal means (25) connected to and controlled by said comparator means in a computer and providing a warning signal output if the comparator determines disconformity in the data read out under predetermined standard or design level voltage conditions and under changed voltage level conditions.

14. System according to claim 8, wherein said operating voltage at the voltage level is applied to said memory (4) upon interrogation or read-out of data.