Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques

• US 4,503,598 A
• Filed: 05/20/1982
• Issued: 03/12/1985
• Est. Priority Date: 05/20/1982
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: Fairchild Camera and Instrument Corporation (ON Semiconductor Corporation)
• Inventors: Vora, Madhukar B., Patel, Vikram M.
• Primary Examiner(s): Saba, Willam G.
• Application Number:
  US06/380,170
• Time in Patent Office: 1,027 Days
• Field of Search: 29/571, 29/578, 29/580, 148/187, 148/190, 357/23 VD, 357/23 S, 357/55, 156/649
• US Class Current: 438/274
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.

The resulting semiconductor structure includes an N type substrate 10, an N type epitaxial layer 12, an opening 21 in the epitaxial layer 12 extending downward a selected distance, an upper N type region 33 surrounding the opening 21 and extending to the surface of the epitaxial layer 12, a lower P type region 30 which extends to the surface of the epitaxial layer 12 and everywhere separates the N type region 33 from epitaxial layer 12, an electrode 40 formed in the opening and extending to the upper surface of the epitaxial layer 12, and a second electrode 18 disposed above epitaxial layer 12 and separated from it by insulating material 15.

Claims

1. A method of fabricating a semiconductor structure comprising:

forming a pair of spaced apart electrically conductive gate electrodes on a semiconductor drain region of first conductivity type, the electrodes being separated from the drain region by a layer of insulating material;

introducing first and opposite conductivity type impurity into the drain region between the spaced apart gate electrodes by using the gate electrodes to mask portions of the drain region to thereby form source and gate regions, respectively, the first conductivity type impurity being everywhere separated from the drain region by the opposite conductivity;

removing a portion of the drain region between the spaced apart gate electrodes to form an opening extending through the source region but not through the gate region;

depositing electrically conductive material into the opening in contact with both of the source and gate regions but not in contact with any of the drain region and not in contact with the gate electrodes; and

providing electrical connections to each of the drain region, the gate electrodes, and the electrically conductive material deposited in the opening.

2. A method as in claim 1 wherein the step of forming a pair of spaced apart electrically conductive gate electrodes comprises:

depositing a layer of polycrystalline silicon on the layer of insulating material; and

removing a region of the layer of polycrystalline silicon to thereby form a pair of spaced apart gate electrodes.

3. A method as in claim 2 wherein following the step of removing a region, a step is performed comprising:

coating each of the pair with insulating material.

4. A method as in claim 3 wherein the step of coating comprises oxidizing the gate electrodes.

5. A method as in claim 3 wherein the additional opposite conductivity type forms an opposite conductivity region beneath the gate region.

6. A method as in claim 1 wherein following the step of removing and prior to the step of depositing a step is performed comprising introducing additional opposite conductivity type impurity into the opening.

7. A method as in claim 6 wherein the step of depositing comprises depositing a metal.

8. A method as in claim 1 wherein the step of introducing first and opposite conductivity type comprises ion implanting first and opposite conductivity type.

9. A method in claim 8 wherein the step of introducing first and opposite conductivity type is followed by a step of diffusing the first and opposite conductivity type.

10. A method as in claim 1 wherein the step of removing portions comprises etching the drain region.

11. A method as in claim 10 wherein the step of etching the drain region comprises etching with a plasma.

12. A method as in claim 1 wherein the step of providing electrical connections further comprises forming the drain region on an underlying more heavily doped semiconductor substrate to thereby provide an electrical connection to the drain region.

13. A method as in claim 1 wherein the first conductivity type is N conductivity type.

14. A method of fabricating a semiconductor structure comprising:

depositing first conductivity type epitaxial silicon having an upper surface on a first conductivity type silicon substrate;

forming a plurality of polycrystalline silicon electrodes on the upper surface of the epitaxial layer but separated therefrom by a layer of silicon dioxide;

introducing first and opposite conductivity type impurities into the epitaxial layer between the electrodes, by using the electrodes and underlying silicon dioxide to mask regions of the epitaxial layer, the opposite conductivity type impurity underlying the first conductivity type impurity;

removing regions of the epitaxial layer between the electrodes to form openings in the epitaxial layer, the openings extending through the first conductivity type but not the opposite conductivity type;

introducing additional opposite conductivity type impurity beneath the existing opposite conductivity type impurity; and

forming metal electrodes in the openings.