Oxide trench structure for polysilicon gates and interconnects

• US 4,503,601 A
• Filed: 04/18/1983
• Issued: 03/12/1985
• Est. Priority Date: 04/18/1983
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: NCR Corporation
• Inventors: Chiao, Samuel Y.
• Primary Examiner(s): Weisstuch, Aaron
• Assistant Examiner(s): Auyang, Hunter L.
• Application Number:
  US06/486,275
• Time in Patent Office: 694 Days
• Field of Search: 29/571, 29/576 W, 29/591, 357/23 HV, 357/23 S, 357/23 CS, 357/23 VD, 357/59, 357/71 P
• US Class Current: 438/303
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 21/8236 Combination of enhancement and depletion transistors
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 438/911 Differential oxidation and etching

Abstract

Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate.

In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation. Then, low temperature thermal oxidation is accomplished growing a thick oxide over the polysilicon gate sidewalls and a thin oxide over the source-drain regions. The mask over the gate and the thin oxide over the source-drain regions is removed and by ion implantation heavily doped source-drain regions are formed in the previously formed lightly doped source-drain regions not masked by the polysilicon sidewall oxide. Selective deposition of a metal is then accomplished over the source-drain regions of the silicon substrate and the polysilicon gate.

Claims

1. A process for forming a metal covered high conductivity region of a substrate and a metal covered polysilicon conductor in close proximity to said region, said process comprising:

forming said polysilicon conductor on selected portions of said substrate from a highly doped polysilicon layer having a masking member thereon;

thermally oxidizing at a relatively low temperature in the range of 700-750 degrees C. for a time sufficient to form a relatively thick oxide layer on the side surfaces of said polysilicon conductor and a relatively thin oxide layer on the uncovered portions of said substrate;

removing the relatively thin oxide layer on said uncovered portions of said substrate;

doping said uncovered portions of said substrate to a high conductivity;

removing the masking member to expose the upper surface of said polysilicon conductor; and

forming a metal layer over said exposed, highly doped portion of said substrate and polysilicon conductor.

2. The process as in claim 1 wherein said masking member is a layer of silicon nitride.

3. A process for forming a lightly doped drain polysilicon gate n-MOSFET on a p-type semiconductor silicon substrate having an active region covered by a relatively thin silicon dioxide layer, said process comprising:

forming a highly doped polysilicon layer over th silicon dioxide layer;

forming a mask over the polysilicon;

patterning the polysilicon in the presence of a mask to form a polysilicon gate on said active region;

removing said oxide layer outside a gate region dfined by said gate on the active region;

implanting n-type ions at a relatively low dose and energy in source and drain regions defined in said active region by the gate and mask thereon;

thermally oxidizing at a relatively low temperature of about 700-750 degrees C. for a time sufficient to form a relatively thick oxide layer on the side surfaces of said polysilicon gate and a relatively thin oxide layer in the previously defined source and drain regions of the substrate;

removing said mask over the polysilicon and said thin oxide over the source and drain regions;

implanting n-type ions of a relatively high dose and energy in said source and drain regions not masked by said thick oxide and said polysilicon gate; and

selectively depositing a metal layer over the exposed polysilicon gate and the source and drain regions.

4. The process as recited in claim 3 further comprising the steps of:

patterning the polysilicon in the presence of the mask to form interconnecting conductors simultaneously with the patterning of the polysilicon into a gate;

forming a thick oxide layer on the side surfaces of the conductors during said thermal oxidation step; and

selectively depositing a metal layer over the polysilicon interconnects during said metal deposition step.