Simulator interface system

• US 4,506,324 A
• Filed: 03/08/1982
• Issued: 03/19/1985
• Est. Priority Date: 03/08/1982
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Healy, Leonard D.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US06/355,400
• Time in Patent Office: 1,107 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 340/825.06
• US Class Current: 703/21
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A linkage between a host computer and a plurality of external devices, suchs a simulator system, utilizes a distributed processing network of individual data processors to process, control, and position data for transmission to and from said host computer on a data rate of change basis. A master processor interfaces with the host computer and is connected via a serial data link to a plurality of slave processors located at the external devices. Each processor determines the necessity for a transfer of data from its associated computer or device and controls data transmission therefrom accordingly.

Claims

1. An intelligent linkage for data transfer between a host computer and external devices where the data to be transferred are variable based on control and status data, comprising in combination:

a microprocessor based master processor having first means coupled to said host computer for controlling data transfer from said host computer to said master processor, first means connected to said first data transfer controlling means for determining changes in data received from said host and determining the appropriate external device associated therewith, first means connected to said said first determining means for communicating said changes in data to said external device via a microprocessor based slave processor, and second means coupled to said host computer and to said slave processor for controlling data transfer from said master processor to said host computer;

said microprocessor based slave processor having third means coupled to said external device for controlling the transfer of status data from said external device to said slave processor, second means connected to said third controlling means for determining changes in said data received from said external device, second means connected to said second determining means for communicating said changes in data to said host computer via said master processor, fourth means coupled to said external device for controlling data transfer from said slave processor to said external device; and

means coupling said second data communicating means of said slave processor and said second controlling means of said master processor, and said first data communicating means of said master processor and said fourth data controlling means of said slave processor, for serial transmission of said data.

2. The linkage of claim 1 wherein said first data transfer controlling means in said master processor comprises:

controller means coupled to said host computer, for providing interface signals to said host computer to cause data transfers and for providing gating and timing signals for said master processor; and

memory map means coupled to said controller means, for providing data to said controller means relating memory locations in said host computer to data type, data location in said slave processor, and data location in said master processor.

3. The linkage of claim 2 wherein said first means for determining changes in data in said master processor comprise:

data memory means connected to said first means for communicating changes in data, for holding the value of the latest data communicated from said master processor to said external device; and

comparator means for determining whether control data input from said host computer matches the data held in said data memory means, connected to receive inputs from said data memory means and said host computer and having an output coupled to said communicating means.

4. The linkage of claim 3 wherein said first data communicating means in said master processor comprises;

a receiver/transmitter means connected to said serial data transmission means for receiving status data from said slave processor while sending control data to said slave processor;

transmit buffer means connected to said comparator means for storing changes in data output by said comparator means and having output coupled to said receiver/transmitter means and said data memory means for transferring data to said data memory means simultaneously with the transfer of said data to said slave processor, thereby updating said data memory means for each transfer of data; and

receiver buffer means connected to said receiver/transmitter means for storing said status data from said slave processor until processed by said master processor and connected to said data memory means and said comparator means for receiving data from said receiver/transmitter means and outputting data to said comparator means and said data memory means.

5. The linkage of claim 1 wherein said first data communicating means in said master processor comprises:

a receiver/transmitter means connected to said serial transmission of data means, for receiving said status data from said slave processor while sending said control data to said slave processor;

transmit buffer means connected to said first determining means and to said receiver/transmitter means, for storing changes in data output by said first determining means; and

receive buffer means connected to said receiver/transmitter means and to said first determining means, for storing data from said slave processor until processed by said master processor.

6. The linkage of claim 1 wherein said second means for determining changes in data received from said external device, comprises:

data memory means connected to said second data communicating means, for holding the latest value of each data transmitted to said host computer from said external device; and

comparator means coupled to said data memory means and to said third controlling means, and to said second data communicating means, for determining whether the value in said data memory means matches the data value received from said external device wherein said received data value is coupled to said comparator means by said data memory means under the control of said third controlling means and the effective output of said comparator means is provided to said second data communicating means.

7. The apparatus of claim 1 wherein said second means for communicating said changes in data comprises:

receiver/transmitter circuitry operably connected to said serial transmission means;

transmit buffer means connected to said receiver/transmitter circuitry for storing the changes in data determined by said second determining means for transmission to said host computer via said master processor; and

receive buffer means connected to said receiver/transmitter and to said fourth data transfer controlling means for storing changes in data from said master processor and slave processor until processed by said slave processor.

8. The linkage of claim 1 wherein said master processor further comprises:

a shared memory including therein a data memory means for holding the latest value of each variable transmitted from said host computer to said external device, and also including a memory map means for relating memory location in said host computer to data type, data location in said slave processor and data location in said data memory;

an interface logic means operably connected to said host computer for generating signals to transfer data between said host computer and said shared memory, having direct memory access to said shared memory;

a controller comprising a first microprocessor with its own private memory and access to said shared memory, wherein said first microprocessor communicates with and controls said interface logic through an input/output connection, and further comprising a plurality of microcomputers, each having a private memory arrayed in a distributed network and connected via direct memory access to said first microprocessor, wherein each said microcomputer has accesss to said shared memory and provides an output to said first microprocessor;

a transmitter coupled to accept data from said private memory of said controller and send said data to the slave processor; and

a receiver coupled to accept data from said slave processor and store said data in the private memory of said controller, and connected to and under the control of said controller, wherein said controller functions to determine said changes in data.

9. The linkage of claim 8 wherein said slave processor comprises:

a slave shared memory including therein a data memory means for holding the latest value of the status data transmitted from said external device to said host computer, and also including a memory map means for relating memory location within the slave processor to memory type, external device address, and data location in the data memory of said master processor;

system cards having said status and control data;

an interface logic means connected to said system cards for generating signals to transfer data between said system cards and said slave shared memory;

a controller comprising a controller microprocessor with its own private memory and access to said slave shared memory, wherein said controller microprocessor communicates with and controls said interface logic through an input/output connection, and further comprising a plurality of microcomputers, each having a private memory arrayed in a distributed network and connected via direct memory access to said controller microprocessor, wherein each said microcomputer has access to said shared memory and provides an output to said controller microprocessor;

a transmitter/receiver memory operably connected to said controller;

a transmitter operably connected between said transmitter/receiver memory and said serial data transmission means for transmitting data in said transmitter/receiver memory to said master processor, wherein said transmitter is coupled to receive said data via direct memory access; and

a receiver coupled to accept data from said master processor and store said data in said transmitter/receiver memory, and connected to and under the control of said controller, wherein said controller functions to determine changes in data received from said external devices.

10. A method of simulation device control under a host computer via an intelligent interface comprising the steps of:

loading a control program into said host computer compatible with said simulation device;

transferring data to said interface from said host computer;

calculating in the interface in cyclic manner an extrapolated data prediction Y_n+1 based on N known prior data points in accordance with the reduced Lagrange polynomial which is ##EQU2## comparing said data prediction to said transferred data in each cycle;

transferring changes in transferred and extrapolated data to said simulator device as control signals;

transferring data to said interface from said simulator device concurrent with said data transfer from said host computer to said interface;

determining in the interface in cyclic manner an extrapolated data prediction Y_n+1 based on N known data points previously supplied from said external device, said determination in accordance with the formula ##EQU3## checking said predicted data point versus said supplied data point for each cycle of operation; and

transmitting changes in said predicted and received data to said host computer as response signals.

11. A method of controlling a simulator device utilizing a preprogrammed host computer, wherein said host computer communicates with said simulator device via an intelligent interface operably connected between the input and output of said host computer and said simulator device, comprising the cyclic steps of:

transferring control data from said host computer to said interface at time 1;

extrapolating in said interface a predicted control data point Y_n+1 based on N known prior data points in accordance with the equation ##EQU4## comparing in said interface said predicted data point to said transferred data at a time 2;

comparing in said interface said transferred data to data transferred in the next preceding cycle;

extrapolating in said interface a new predicted control data point based on said transferred control data and said equation;

transmitting changes in said control data or said predicted control data to said simulator device as control symbols at time 3;

transferring status data from said simulator to said interface at time 1;

extrapolating in said interface a predicted status data point, Y_n+1, based on N known status data points and said equation;

comparing in said interface said predicted status data and said transferred status data at time 2;

comparing in said interface said transferred status data to data transferred to said interface in the next preceding cycle;

comparing in said interface said predicted status data to data predicted in the next preceding cycle;

transmitting via said interface to said host computer any changes in predicted or transferred status data at time 3; and

verifying in said interface correlation between input control data and status data at time 4.