Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation
First Claim
1. In an I/O controller having interfaces for transferring data between a host processor system and one or more peripheral devices, an improved interface adapter comprising:
- format conversion circuit means connectable in various configurations between said host processor and devices for transferring data between said processor and devices in various bit width-parallel formats;
multi-state control means dedicated exclusively for controlling said format conversion circuit means; and
means responsive to various transfer initiating signals produced under the direction of supervisory programs executed in said host system for variably conditioning said control means to sequence autonomously through various series of control states for causing said conversion circuit to transfer data between said host processor and said devices in various bit width-parallel formats pre-defined by said signals.
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Accused Products
Abstract
This adapter contains two separately controllable sections, each transferring data in various formats between a peripheral device interface and either a microprocessor contained in an associated I/O controller or a host processor or both. Dedicated controls enable the adapter to operate autonomously after being prepared by the microprocessor. Separate but interconnectable handshaking controls enable the sections to operate either asynchronously or in time coordination with each other. Handshaking controls in plural adapters are interconnectable to coordinate related transfers of data between a device and one or more hosts via plural adapter paths. Programmable commands enable the microprocessor to condition the adapter to conduct various data transfers autonomously. Such data can be transferred to or from the device interface in various bit-parallel formats defined by the commands, and from or to the host processor, the microprocessor, or both the host processor and microprocessor concurrently. In one handshaking mode, the adapter sustains an array indexing operation in which one section transfers "address" data to a device and the other section transfers "addressed" portions of a data array between the same device and either the host processor or the microprocessor.
123 Citations
12 Claims
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1. In an I/O controller having interfaces for transferring data between a host processor system and one or more peripheral devices, an improved interface adapter comprising:
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format conversion circuit means connectable in various configurations between said host processor and devices for transferring data between said processor and devices in various bit width-parallel formats; multi-state control means dedicated exclusively for controlling said format conversion circuit means; and means responsive to various transfer initiating signals produced under the direction of supervisory programs executed in said host system for variably conditioning said control means to sequence autonomously through various series of control states for causing said conversion circuit to transfer data between said host processor and said devices in various bit width-parallel formats pre-defined by said signals.
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2. In an I/O controller having interfaces for transferring data between a host processor system and one or more peripheral devices, an improved adapter comprising:
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first and second discretely separate format conversion circuit sections connectable in parallel between said host and device interfaces in various width bit-parallel formats; multi-state control means dedicated exclusively for controlling said circuit sections; and means responsive to signals from said host system for applying command signals to said control means for defining various data transfer operations and associated bit-width formats; said control means sequencing autonomously through various series of control states, in response to said applied command signals, for selectively causing one or both of said circuit sections to transfer various length blocks of data between said host system and a device in various width bit-parallel formats defined by the applied signals. - View Dependent Claims (3, 4, 5)
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6. In an I/O controller for transferring data between a host processor and one or more devices in various formats, said controller containing a microprocessor for interpreting commands prepared by said host processor and a cycle stealing bus circuit for transferring data between said host processor and devices in an autonomous manner after being prepared by said microprocessor, an improved peripheral interface adapter comprising:
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data transfer means for transferring data between said devices and either said microprocessor or said cycle stealing bus circuit or both said microprocessor and said bus circuit concurrently; control means dedicated exclusively for controlling said data transfer means; and means for applying various control signals from said microprocessor to said control means for causing said control means to operate autonomously to direct said data transfer means to transfer various amounts of data in various bit-parallel formats, between a device and either said microprocessor or said bus circuit or both said microprocessor and said bus circuit at the same time. - View Dependent Claims (7, 8, 9)
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10. In an I/O controller containing an integral microprocessor for interpreting I/O commands prepared by a host processor, and a bypass bus circuit conditionable by said microprocessor for autonomously transferring varied-length data records between said host processor and one or more devices in a cycle stealing mode, an improved adapter for interfacing between said devices and said bus and microprocessor, comprising:
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sectionable register means for staging data in transit between a device and either said microprocessor for said bus circuit or both in bit-parallel groups of varying bit widths; and means for variously connecting sections of said register means to said microprocessor and bus circuit for permitting data to be transferred between said device and either said host processor or said microprocessor, or both, in various bit-width bit-parallel formats.
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11. In an I/O controller containing an integral microprocessor for interpreting commands prepared by a host processor and containing a bypass bus circuit conditionable by said microprocessor for autonomously operating to transfer varied-length data records between said host processor and one or more devices in a cycle stealing mode, an improved interface adapter comprising:
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means for staging data for bit-parallel transfer to or from a said device in various bit-width parallel formats; and selective connecting means for connecting said staging means variously with said bus circuit and/or said integral microprocessor for exchanging data with said host processor and microprocessor in various bit-width parallel formats.
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12. In an I/O controller packageable on an LSI circuit card, said controller integrally containing a microprocessor for interpreting commands prepared by a host processor, and a cycle stealing bus circuit having dedicated controls conditionable by said microprocessor in response to various said commands for operating autonomously to transfer data between said host processor and a peripheral device interface, an improved interface adapter for transferring data in various bit-parallel formats between said device interface and either said bus circuit or said microprocessor or both, comprising:
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register means having discretely separate first and second sections, each connectable for transferring data bidirectionally between said device interface and said bus circuit, one of said sections being connectable to said microprocessor only for transferring data unidirectionally from said microprocessor to said device interface and the other section being connectable to said microprocessor only for transferring data unidirectionally to said microprocessor from said device interface; and multi-state control means dedicated exclusively for controlling operations of said register means, said control means containing sequence control means responsive to various command signals from said microprocessor for operating said sequence control means through various sequences of states, and handshaking control means variously connectable to said device interface for causing data to be transferred bidirectionally between said register means sections and said device interface in various width bit-parallel formats; said handshaking means comprising discrete first and second sets of request and acknowledge circuits, means for selectively interconnecting the acknowledge circuit in the first set with either a device via said interface or the request circuit in the second set, and means for connecting the request circuit of the first set and the acknowledge circuit of the second set to said device.
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Specification