Semiconductor memory device with pipeline access

• US 4,509,142 A
• Filed: 12/15/1982
• Issued: 04/02/1985
• Est. Priority Date: 12/15/1982
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Childers, Jimmie D.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/449,959
• Time in Patent Office: 839 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/169
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A semiconductor memory device contains an on-chip self-incrementing counter which may be loaded from address input terminals, so that the memory cell array may be accessed using either an incoming address or the last address incremented by one. Also, the incremented last address is saved in a latch. A comparator receives the present address and incremented last address, and if these match a data output is available immediately. After a read cycle, the array is always accessed using the incremented last address, so when another fetch is initiated from the CPU, if it is for the next sequential address, the data is already available in a data ouput latch and the apparent access time is much less than that of the memory array.

Claims

1. A memory drive comprising:

an array of memory cells;

accessing means for reading selected data from the array based upon a read address and for storing such data in a data latch;

a counter with means for incrementing the counter;

input address terminals for the device;

a comparator;

coupling means applying an input address from said terminals to said counter, to said accessing means and to one input of said comparator;

an address latch having an input connected to receive the incremented contents of the counter an output connected to an input of the comparator;

and means for activating either said accesssing means or said data latch in response to an output of the comparator.

2. A device according to claim 1 wherein the accessing means includes decoder means and a plurality of sense amplifiers.

3. A device according to claim 1 wherein the array includes rows and columns of dynamic one-transistor memory cells, and the accessing means includes row decoder means and column decoder means.

4. A device according to claim 3 constructed as a single integrated semiconductor unit.

5. A memory device comprising an array of memory cells, an address input to the device for connection to external means, a data output from the device for connection to external bus means, a data latch coupling an output of the array to said data output, control terminals for the device for connection to external control lines for transfer of control signals, and addressing means within the device coupling said address input to the array;

said addressing means comprising;

a counter having an input coupled to said address input, with means for incrementing the counter,

a comparator having first and second inputs and a compare output, the first input being connected to receive the incremented output from the counter,

an address latch connected to receive the incremented output of the counter, an output of the address latch coupled to the second input of the comparator,

a control output to one of said control terminals to signal that valid data is presented to said data output,

and means responsive to said compare output to activate the data latch and the control output.

6. A device according to claim 5 wherein the array of the memory device is an array of dynamic one-transistor memory cells, and the memory device is a single semiconductor integrated circuit.

7. A device according to claim 5 wherein an output of the address latch is coupled to an input of the counter.

8. A device according to claim 5 wherein one of said signals on the control lines is an enable signal from a processor means to the memory device, and said comparator operates only upon receipt of the enable signal.

9. A device according to claim 8 wherein prior to said enable signal the data latch contains data from the array derived from addressing the array with said incremented output from the counter.

10. A processor system comprising:

processor means having address and data bus means and control lines and functioning to send out addresses on said bus means and to receive data from the bus means under control of signals on said control lines;

a memory device having an array of memory cells, an address input to the device connected to said bus means, a data output from the device connected to said bus means, a data latch coupling an output of the array to said data output, control terminals for the device connected to said control lines, and addressing means within the device coupling said address to the array;

said addressing means comprising;

a counter having an input coupled to said address input, with means for incrementing the counter,

a comparator having first and second inputs and a compare output, the first input being connected to receive the incremented output from the counter,

an address latch connected to receive the incremented output of the counter, an output of the address latch coupled to the second input of the comparator,

a control output to one of said control terminals to signal that valid data is presented to said data output,

and means responsive to said compare output to activate the data latch and the control output.

11. A system according to claim 10 wherein the array of the memory device is an array of dynamic one-transistor memory cells, and the memory device is a single semiconductor integrated circuit.

12. A system according to claim 10 wherein an output of the address latch is coupled to an input of the counter.

13. A system according to claim 10 wherein one of said signals on the control lines is an enable signal from the processor means to the memory device, and said comparator operates only upon receipt of the enable signal.

14. A system according to claim 13 wherein prior to said enable signal the data latch contains data from the array derived from said incremented output from the counter.

15. A system according to claim 14 wherein the counter is incremented after said enable signal is no longer present and the data latch is loaded with data from the array based upon addressing the array with the incremented counter output.