Semiconductor memory device

• US 4,509,148 A
• Filed: 05/11/1983
• Issued: 04/02/1985
• Est. Priority Date: 10/04/1979
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Asano, Masamichi, Iwahashi, Hiroshi
• Primary Examiner(s): Popek, Joseph
• Application Number:
  US06/493,605
• Time in Patent Office: 692 Days
• Field of Search: 365/230, 365/189, 365/226
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of said row decoders for controlling the conduction state of the switching MOS transistors.

Claims

1. An address designation circuit responsive to externally-generated address signals and comprising:

a plurality of first decoding circuits coupled to said address signals;

a plurality of second decoding circuits coupled to said address signals; and

a plurality of buffer circuits each including a plurality of buffers having first and second input terminals, said first input terminals of the buffers in each of said buffer circuits being commonly connected to an output of a different one of said plurality of said first decoding circuits, and said second input terminals of each buffer in each buffer circuit being connected to an output of a different one of said plurality of said second decoding circuits.