Receiver for multicarrier signals protected from unwanted signals

• US 4,509,206 A
• Filed: 05/02/1983
• Issued: 04/02/1985
• Est. Priority Date: 05/04/1982
• Status: Expired due to Fees

• Current Assignee: Thomson-CSF (Thales SA)
• Original Assignee: Thomson-CSF (Thales SA)
• Inventors: Collin, Claude, Pontif, Marc, Carpe, Michel
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US06/490,513
• Time in Patent Office: 701 Days
• Field of Search: 455/234, 455/245, 455/246, 455/247, 455/250, 455/251, 455/253, 455/249, 455/17, 455/206, 455/296, 455/303, 455/311, 375/98, 375/102
• US Class Current: 455/234.2
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01

Abstract

The invention relates to a multicarrier signal receiver protected against unwanted signals. Between the high frequency circuit and the intermediate frequency circuit, it has a frequency-selective attenuation and preselection circuit, while a circuit for detecting the disturbed channels is coupled to the demodulation circuit and supplies control signals characteristic of the appearance and disappearance of the unwanted signals. The receiver also comprises a control circuit eliminating the disturbed channel for processing demodulated signals and for the automatic control of the intermediate frequency amplifier circuit, and controlling the attenuation of the disturbed channel in the selective attenuation circuit.

Claims

1. A multicarrier signal receiver comprising a high frequency circuit for receiving a plurality of modulated carrier signals and having an output providing a corresponding plurality of modulated intermediate frequency carrier signals, a circuit for the preselection and selective attenuation of the intermediate frequency carrier signals comprising a plurality of filters tuned to the intermediate frequency carrier signals, whose inputs are connected to the output of the high frequency circuit and whose outputs are connected to respective attenuators, each having a control input and an output, an adder responsive to said attenuator outputs and having a sum output, an intermediate frequency amplification circuit having an input connected to the output of the adder, and an output, a demodulation circuit comprising a plurality of signal demodulation paths have one path for each modulated intermediate frequency carrier signal respective, each path including a filter connected to the output of the intermediate frequency amplification circuit, in series with a detector-amplifier and a demodulator, each path further including an elementary detection circuit for detecting an unwanted or interfering signal having an input connected to the output of a respective demodulator and an output supplying a control signal characteristic of an appearance or disappearance of an unwanted signal for the corresponding carrier signal, the output of the detection circuit associated with a particular carrier signal being coupled to the control input of the corresponding attenuator.

2. A receiver according to claim 1, wherein the intermediate frequency amplifier is controlled by an automatic gain control circuit having inputs coupled to the outputs of detector amplifiers and whose output provides the highest detected voltage present on said detector-amplifier outputs, wherein said receiver also comprises, between the outputs of the detector amplifiers and the inputs of the automatic gain control circuit, a first set of switches having electronic control inputs connected to the outputs of the plurality of elementary detection circuits for preventing the transmission of a detected voltage related to a disturbed channel to the AGC circuit.

3. A receiver according to claim 2 further comprising a second set of switches having respective inputs and outputs and having electronic control inputs connected to the respective outputs of the detection circuits, said inputs connected to respective outputs of the demodulators circuit and their outputs providing only desired signals.

4. A receiver according to claim 1, wherein an elementary detection circuit comprises a circuit for the recovery and detection of a clock signal having an input connected to the corresponding output of the demodulation circuit, a comparator having two inputs connected to the output of the corresponding detector-amplifier and to the output of the clock signal detection circuit, and a control circuit having an input connected to the output of the comparator and an output constituting the output of the elementary detection circuit which, on the basis of the relative levels of the clock signal and a detector-amplifier output signal, supplies the corresponding control signal.

5. A receiver according to claim 1, wherein the attenuators are enabled to attenuated in response to closing of switches controlled by said control signals.

6. A receiver according to claim 1, wherein the attenuators provide, during the appearance of an unwanted signal on the corresponding carrier, a variable attenuation bringing the amplitude of the unwanted signal to the input of the intermediate frequency amplification circuit to a level related to signal dynamics of the undisturbed channels, the attenuators being enabled to attenuate in response to closing of switches controlled by said control signals said switches applying a variable amplitude voltage signal to the attenuators.

7. A receiver according to claim 6, wherein the receiver comprises, for each channel, a circuit for comparing the level of a detected carrier and the level of an undisturbed maximum level detected carrier, whose output provides said variable amplitude voltage signal.