Single mask process for fabricating CMOS structure

• US 4,509,991 A
• Filed: 10/06/1983
• Issued: 04/09/1985
• Est. Priority Date: 10/06/1983
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Taur, Yuan
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/539,516
• Time in Patent Office: 551 Days
• Field of Search: 148/1.5, 148/187, 29/571, 29/576 B, 29/578, 357/42, 357/91
• US Class Current: 438/232
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

A process for forming self-aligned complementary n⁺ and p⁺ source/drain regions in CMOS structures using a single resist pattern as a mask to form both the n⁺ channel implant and then the p⁺ channel implant. The resist pattern is formed using conventional lithography techniques to form an implant mask which covers the p⁺ channel region while the n⁺ source and drain regions are ion implanted. The resist mask is then used as a lift-off mask in order to cover the n⁺ channel region while the p⁺ source and drain regions are ion implanted.

Claims

1. A process for implanting self-aligned source and drain regions in a complementary semiconductor structure of the type including a semiconductor substrate having recessed oxide isolation regions, defining at least one pair of device regions, a well region in said semiconductor substrate below one of said device regions, and gate electrodes in said device regions between said recessed oxide regions, said process comprising the steps of

(a) first depositing a layer of photoresist on the surface of said substrate and exposing said photoresist layer through a single lighographic mask, and etching openings in said photoresist layer in accordance with said single lithographic mask such that source and drain regions of a first device region of said at least one pair of device regions are covered by a discrete layer of said photoresist and source and drain regions of a second device region of said at least one pair of device regions adjacent to said first device region are located under said opening in said photoresist layer,

(b) implanting ions of a first conductivity type into said surface of said substrate through said opening in said photoresist layer to form ion implanted source and drain regions in said second device region, implantation of ions into said first device region being blocked by said photoresist layer,

(c) depositing a layer of ion implantation blocking material over said photoresist layer and through said openings in said photoresist layer onto said source and drain regions of said second device region of said substrate,

(d) removing said photoresist layer, thereby exposing said source and drain regions of said first device region of said substrate and maintaining said source and drain regions of said second device region covered by said ion implantation blocking material in a pattern which is the reverse of its first pattern of said photoresist layer in said single photolithographic masking step (a),

(e) and implanting ions of a second conductivity type into said surface of said substrate for forming ion implanted source and drain regions in said first device region, ion implantation of said second device region being blocked by said layer of ion implantation blocking material such that said source/drain regions of said first device region and said source/drain regions of said second device region are directly self-aligned.

2. A process for implanting self-aligned source and drain regions in a complementary semiconductor structure according to claim 1 wherein said ions implanted in said step b are n⁺ conductivity ions to form n-channel source/drain regions and wherein said well is an n-well.

3. A process for implanting self-aligned source and drain regions in a complementary semiconductor structure according to claim 1 wherein said ions implanted in said step e are p⁺ conductivity ions to form p-channel source/drain regions.

4. A process for implanting self-aligned source and drain regions in a complementary semiconductor structure according to claim 1 wherein ions implanted in step b are also implanted through an opening in said resist layer adjacent to said covered first device region, said implanted ions forming a first conductivity ohmic contact to said well region.

5. A process for implanting self-aligned source and drain regions in a complementary semiconductor structure according to claim 1 wherein ions implanted in step e are also implanted into said substrate surface in an area adjacent to said second device region not covered by said ion implantation blocking material to form an ohmic contact to said substrate.

6. A process for implanting self-aligned source and drain regions in a complementary semiconductor structure according to claim 1 wherein said ions implanted in step b are n⁺ conductivity ions of arsenic or its equivalent, and wherein said ions implanted in step b are p⁺ conductivity ions of boron or its equivalent.

7. A process for implanting self-aligned source and drain regions in a complementary semiconductor structure according to claim 6 wherein said ion implantation blocking material of step c is silicon or its equivalent.