Stepping motor controller

• US 4,510,266 A
• Filed: 10/04/1982
• Issued: 04/09/1985
• Est. Priority Date: 10/08/1981
• Status: Expired due to Fees

• Current Assignee: Oce-Nederland B.V. (Canon Inc.)
• Original Assignee: Oce-Nederland B.V. (Canon Inc.)
• Inventors: Eertink, Bastiaan B. B.
• Primary Examiner(s): Shoop, William M.
• Assistant Examiner(s): BERGMANN, SAUL
• Application Number:
  US06/432,631
• Time in Patent Office: 918 Days
• Field of Search: 365/230, 365/233, 365/236, 365/239, 318/696, 318/685
• US Class Current: 318/696
• CPC Class Codes: H02P 8/18 Shaping of pulses, e.g. to reduce torque ripple Reducing overshoot H02P8/32 takes precedence

Abstract

Pulses from a fixed-frequency pulse generator are counted in a pulse counter to produce a binary number. The binary number is employed to access successive memory addresses which contain data for producing drive pulses for a stepping motor. The memory contents are arranged so that the number of pulses from the pulse generator required to produce a drive pulse decreases during starting and increases during stopping so that smooth acceleration and deceleration of the stepping motor are achieved. In one embodiment, successive locations store "0" or "1" to produce a motor drive signal. In another embodiment, successive locations store numbers which control the length of time until the next drive signal is produced.

Claims

1. Apparatus for generating signal pulses for controlling a stepping motor, comprising:

a pulse generator effective for producing a substantially constant frequency pulse signal;

a memory having a multiplicity of successively addressable memory locations, each of said memory locations having a content;

addressing means responsive to said pulse signal for successively addressing said memory locations;

said memory comprising output means responsive to the respective contents of said memory locations as they are addressed successively by said addressing means for producing electrical signals having frequencies to control said stepping motor; and

said contents being arranged to produce in response to said addressing at least one of an increase in the frequency of said electrical signals for starting of said stepping motor and a decrease in said frequency thereof for stopping of said stepping motor.

2. Apparatus according to claim 1, wherein each of said memory locations contains either a "0" or a "1" and said memory locations are arranged in multiple sets of memory locations including sets thereof in which the respective memory locations have the same content and sets thereof having different numbers of memory locations, the number of memory locations in a set thereof controlling a time during which said memory output means maintains a state produced by a said content.

3. Apparatus according to claim 2, wherein said addressing means includes a counter, said counter being effective to produce a changing digital number in response to said pulse signal, each value of said digital number being applied to a related one of said memory locations.

4. Apparatus according to claim 1, 2, or 3, wherein said memory locations include a subset thereof in which the content of at least one of the subset memory locations differs from that of at least one other of them and said addressing means is effective to repetitively address through said subset of memory locations to produce a predetermined substantially constant frequency of said electrical signal, said predetermined frequency being lower than said pulse signal frequency.

5. Apparatus according to claim 1, wherein said addressing means includes at least one UP/DOWN counter and means for controlling said at least one UP/DOWN counter to count one of up and down during acceleration of said stepping motor and to count the other of up and down during deceleration of said stepping motor, each said content including a bit effective to control a signal state of said memory output means, said contents being arranged in successive sets of said memory locations including sets thereof containing bits of one type alternating with sets thereof containing bits of another type, at least some of said sets progressively decreasing in length when addressed in a first sequence for deceleration of said stepping motor and progressively increasing in length when addressed in a second sequence for deceleration of said stepping motor.

6. Apparatus according to claim 5, further comprising means for producing in succession two signal states of said memory output means with a fixed ratio of output signals to pulses of said pulse signal for constant speed running of said stepping motor and means for maintaining said fixed ratio at least to a beginning of deceleration from said constant speed running.

7. Apparatus according to claim 1, wherein said memory locations include first sets of memory locations having a first signal state arranged in alternation with second sets of memory locations having a second signal state, the respective numbers of memory locations in the sets of at least one of said first sets and said second sets changing progressively with change in address.

8. Apparatus according to claim 7, further comprising means operative when the memory locations of said first sets and said second sets have been addressed to continue said addressing means active for repetitively addressing a limited subset of said memory locations and thereby producing said signals at a substantially constant frequency.

9. Apparatus according to claim 8, wherein said subset includes a fixed number of memory locations having said first signal state and a fixed number of memory locations having said second signal state.

10. A stepping motor controller according to claim 1, further comprising means for stopping said pulse generator at an end of stopping of said stepping motor.

11. Apparatus according to claim 1, wherein said contents comprise in each of said memory locations a digital number which in response to a corresponding number of pulses of said pulse signal determines a duration of a signal state of said electrical signals.

12. A method of producing signal pulses for controlling a stepping motor, comprising:

storing a content in each of a multiplicity of memory locations in an addressable memory;

successively addressing said memory locations; and

producing from certain sets of said memory locations as they are addressed, according to respective contents of said sets, output signals for driving said stepping motor;

said sets of memory locations including first sets thereof having a first signal state alternating with second sets of memory locations having a second signal state, at least one of said first sets and second sets containing in the respective sets thereof numbers of said memory locations which change progressively with increasing address whereby said output signals are produced at a frequency that changes with increasing address for correspondingly changing the speed of said stepping motor.

13. A method of producing signal pulses for controlling a stepping motor, comprising:

storing a content in each of a multiplicity of addressable memory locations;

said content in each memory location having one of at least first and second possible signal states;

generating control pulses at a predetermined frequency;

counting said control pulses in an UP/DOWN counter and producing from it signals for successively addressing said addressable memory locations;

the contents of said memory locations being arranged in first sets of contiguous addresses having said first signal state alternating with second sets of contiguous addresses having said second signal state, with the number of addresses in the respective sets of at least one of said first sets and said second sets changing progressively with change in said addresses;

applying said signals from said UP/DOWN counter to said memory locations successively in the one of the up and down directions in which said number of addresses decreases; and

producing in response to the respective signal states of said sets of addressed memory locations output signals at increasing frequency whereby the speed of said stepping motor is increased during starting thereof.

14. A method according to claim 13, and after said starting repetitively addressing a subset of said memory locations including at least one memory location the content of which has said first signal state and at least one memory location the content of which has said second signal state to produce output signals at a rate corresponding to a required running speed of said stepping motor.

15. A method according to claim 13 or 14, further comprising applying said signals from said UP/DOWN counter successively to said memory locations of said first sets and said second sets in the other of said directions, in which said number of addresses increases, to produce signal pulses at decreasing frequency for stopping said stepping motor;

and thereafter cutting off said counter signals to maintain said stepping motor in a stopped condition.