Signature analysis system for testing digital circuits

• US 4,510,572 A
• Filed: 12/28/1981
• Issued: 04/09/1985
• Est. Priority Date: 12/28/1981
• Status: Expired due to Fees

• Current Assignee: Data I/O Corporation
• Original Assignee: Data I/O Corporation
• Inventors: Martin, Robert G., Reece, John M., Franzel, John R.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/334,880
• Time in Patent Office: 1,198 Days
• Field of Search: 364/481, 364/489, 364/579, 371/25, 324/73 R, 324/73 AT
• US Class Current: 714/732
• CPC Class Codes: G01R 31/31914 Portable Testers
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response

Abstract

A signature analyzer for testing digital circuits. The analyzer includes a memory which is initially programmed with a set of signatures characterizing the digital signals on the nodes of a correctly operating circuit. The nodes of a test circuit are then sequentially applied to a signature generator formed by a multi-stage shift register having the outputs of selected stages fed back to a gate to which the digital signal is applied. The signature generated by the shift register is compared to each of the signatures stored in memory until a signature match is found, thus indicating that the digital circuit, at least as far as the test node is concerned, is operating correctly. The signature generated by the shift register consists of twenty-four bits to provide a probability of error which is comparable to the probability of error in comparing a sixteen-bit signature with the signature from a specifically identified node. At the conclusion of a gate period, sixteen bits of the signature are displayed as four hexedecimal digits. In order to minimize the probability of error, the analyzer also counts the number of transitions of the digital signal during the gate period and compares the count to transition counts stored in memory for the digital signals on the nodes of a correctly operating circuit. A comparison is then made of the transition count at the test node with each of the transition counts stored in memory. The analyzer thus ensures a transition count match as well as a signature match.

Claims

1. A system for testing a digital circuit, comprising:

signature generation means receiving a digital signal from a node of said circuit for generating a signature word from said digital signal by combining each of a selected plurality of bits of said digital signature with preselected other ones of the selected plurality of bits of said digital signal;

control means for allowing said signature generation means to respond to said digital signal during a gate period which is synchronized to the operation of said digital circuit so that, at the conclusion of said gate period, said signature generation means provides a signature which characterizes said digital signal during said gate period;

signature memory means for storing respective signatures from a plurality of nodes of said digital circuit indicative of the digital signals on the nodes of said digital circuit when it is operating correctly during said gate period; and

signature comparator means comparing the signature from said signature generation means with the signatures stored in said memory means until either a positive comparison is found or no positive comparison has been found after all of the signatures stored in said memory means have been compared, said signature comparator means generating a signature found indication in response to said positive comparison in response to all of said signatures being compared without a positive comparison.

2. The system of claim 1, further including means for programming said memory means with signatures from a digital circuit known to be operating correctly, said means including a programmer receiving signatures from said signature generation means as the digital signals from each node are applied to said signature generation means during said gate period, said programmer means further applying coded data signals and respective addresses to said memory means corresponding to said signatures.

3. The system of claim 2, further including verifying means for causing said comparator means to compare the output of said signature generation means with the signatures in said memory means before the signature from said signature generation means is written into said memory means and, in the event that the signature from said signature generation means is already stored in said memory means, for preventing the operation of said programming means and generating an indication so that duplicate signatures from the same node are not recorded in said memory means.

4. The system of claim 3, further including means for counting the number of signatures stored in said memory means and providing a visual indication thereof in order to facilitate verification that signatures from all nodes of said circuit have been stored in said memory means.

5. The system of claim 1 wherein said control means generate said gate period in response to a START signal from said digital circuit and terminate said gate period in response to a STOP signal from said digital circuit, said control means further including means for preventing said signature generation means from responding to said digital signal during said gate period responsive to a DISABLE signal from said digital circuit.

6. The system of claim 1, further including means for displaying an unstable signature comprising storage means connected to the output of said signature generation means for recording a signature, second comparator means for comparing subsequent signatures from said signature generation means with the signature recorded in said storage means, and means for continuously displaying any signature from said signature generation means which is not identical to the signature recorded in said storage means.

7. The system of claim 6 wherein said storage means records the signature from said signature generation means each time a new signature is generated and after said comparison is made by said second comparator means so that successive signatures are compared to each other.

8. The system of claim 1, further including automatic reset means for allowing repetitive signature comparisons from a plurality of different nodes while automatically resetting said system after each comparison, comprising:

latch means actuated by said comparison means for recording the signature from said signature generation means responsive to a match between said signature and one of the signatures stored in said memory means;

display means for visually displaying the signature recorded in said latch means; and

signal detection means for determining when said signature generation means is receiving a digital signal from a node of said circuit and for applying an ENABLE signal to said control means to allow said signature generation means to generate a new signature and for applying a reset signal to said latch means to allow said latch means to record the next signature from said signature generation means that matches a signature stored in said memory means.

9. The system of claim 1, further comprising:

transition counter means for counting the number of transitions of said digital signal occurring during said gate period;

transition count memory means for storing respective transition counts from a plurality of nodes of said digital circuit indicative of digital signals on the nodes of said digital circuit when it is operating correctly during said gate period;

transition count comparator means receiving transition counts from said transition counter means and from said transition count memory means for generating a positive comparison indication responsive to a match between the transition count from said transition counter means and any one of the transition counts stored in said transition count memory means, said transition count comparator means generating an indication responsive to a match between both transition counts and signatures during said gate period.

10. The system of claim 1, further including indicator means connected to said comparator means for providing an indication in the event that the signature from said signature generation means matches none of the signatures stored in said signature memory means.

11. An apparatus for testing a digital electronic circuit, comprising:

input means for receiving an digital signal from a selected location in said digital electronic circuit;

clock means for delivering a series of clock pulses, each pulse being coincident with a bit of said digital signal;

signature generation means connected to said input means and said clock means for generating a signature word from said digital signal by combining of a selected plurality of bits in said digital signal with preselected other ones of said selected plurality of bits of said digital signal;

trigger means connected to said digital electronic circuit and connected to said signature generation means for initiating the generation of a signature word in response to a predetermined trigger signal from digital electronic circuit at the start of a gate period;

stop means connected to said signature generation means for terminating the generation of a signature word at the end of said gate period;

memory means for recording a set of signature words corresponding to the digital signals at a set of selected locations of said digital electronic circuit when said digital electronic circuit is operating correctly during said gate period; and

comparator means for comparing the signature word generated by said signature generation means with the signature words recorded in said memory means and for providing an indication of the results of said comparisons.

12. The apparatus of claim 11, further including indicator means connected to said comparator means for providing an indication in the event that the signature from said signature generation means matches none of the signatures stored in said memory means.

13. The apparatus of claim 11, further including means for programming said memory means with signature words from a set of selected locations of a digital circuit known to be operating correctly, said means receiving signature words from said signature generation means as the digital signals from each selected location are applied to said signature generation means and for writing said signature words into respective locations in said memory means in response thereto.

14. The system of claim 13, further including verifying means for causing said comparator means to compare the signature words from said signature generation means with the signature words in said memory means before the signature words from said signature generation means are written into said memory means and, in the event that said signature word from said signature generation means is already stored in said memory means, for preventing the operation of said programming means and generating an indication so that duplicate signature words from the same selected location are not recorded in said memory means.

15. The apparatus of claim 14, further including means for counting the number of signatures stored in said memory means and providing a visual indication thereof in order to facilitate verification that signatures from all nodes of said circuit have been stored in said memory.

16. A method of testing a digital circuit, comprising:

recording a set of signatures which correspond to the signatures on a set of nodes of said circuit when it is operating correctly during a predetermined gate period that is synchronized to the operation of said circuit;

generating a signature from a data stream present on a test node of said circuit taken from said set of nodes during said gate period; and

comparing the signature on said test node to each recorded signature without regard to the identity of said test node until a match is found, thereby indicating the correct operation of said circuit.

17. The method of claim 16, further including the steps of:

recording a set of transition counts which correspond to the number of transitions of respective digital signals on a set of nodes of said circuit when it is operating correctly during said predetermined gate period;

counting the number of transitions on said test node during said gate period; and

comparing the count of transitions on said test node to each recorded transition count without regard to the identity of said test node until a match is found and then determining whether the node corresponding to the recorded transition count which matches the transition count on said test node is identical to the node corresponding to the recorded signature which matches the signature on said test node.