High speed buffer allocation apparatus

• US 4,510,581 A
• Filed: 02/14/1983
• Issued: 04/09/1985
• Est. Priority Date: 02/14/1983
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: Prime Computer, Inc. (DR Holdings, Inc. of Delaware)
• Inventors: Cohen, Paul B.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/466,079
• Time in Patent Office: 785 Days
• Field of Search: 364/900 MS File
• US Class Current: 711/119
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Abstract

A high speed data buffer array allocation circuit is provided in association with a plurality of buffer memories for directing high speed data into the memories. The circuitry employs high speed MOS technology to implement high speed switching and data allocation. The data packet input, generally from an uninterruptible source, is directed and written into a first available buffer memory. The memory can thereafter be read by a host computer. Flags are set indicating the availability of the memory for reading. The data buffer allocation circuit has a plurality of selection circuits connected in an ordered linear array for effectively passing therethrough to the circuit associated with the first available buffer, a data ready input signal. In response to the data ready input signal, the selection circuit and associated gating circuit provide the necessary control to direct the data to the associated memory and to thereafter leave a flag indicating the availability of data. The selection circuit further latches a pass-through element of the circuit to a conductive state whereby the next data ready input signal is passed to a succeeding buffer along said array. When data is read by, for example, the host computer, the buffer selection circuit returns to an operating state wherein the data ready signal is isolated from succeeding selection circuits and the data available flag is removed.

Claims

1. A data buffer array allocation circuit for directing incoming data to an available one of a plurality of buffer memories, said circuit comprising

a plurality of buffer selection circuits, each selection circuit being associated with one of said buffer memories and having

a clear input line,

a data ready input line,

a data ready output line, and

a buffer available line,

means for connecting said selection circuits in an ordered linear array, the data ready output line of an earlier buffer selection circuit of the linear array being connected to the data ready input line of a next succeeding buffer selection circuit, and

each said buffer selection circuit further comprising

means responsive to said data ready input line and said buffer available line, and

operable in a first state for effectively connecting said data ready input line to said data ready output line when said associated buffer has available data therein, and

operable in a second state for effectively isolating said data ready input line from said data ready output line when said associated buffer has no available data therein,

means responsive to an activating clear signal applied over said clear input line for setting said buffer available line to a signal indicating the absence of data in the associated buffer, and

means responsive to a data ready signal on said data ready input line for setting said buffer available line from said signal indicating the absence of data to a signal indicating the availability of data.

2. The data buffer array allocation circuit of claim 1 further comprising

means for directing an incoming data packet into the one of said plurality of buffer memories which is associated with the first buffer selection circuit in the ordered array wherein the ready input and ready output lines are effectively isolated from each other.

3. The data buffer array allocation circuit of claim 2 further wherein said directing means comprises

circuit means connected to the data ready input and data ready output lines of each buffer selection circuit for controlling the input of data to each associated buffer memory.

4. The data buffer array allocation circuit of claim 2 further wherein said directing means comprises

circuit means connected to the buffer available line of each buffer selection circuit for controlling the input of data to each associated buffer memory.

5. The data buffer allocation array circuit of claim 1 wherein said input line and buffer available line responsive means further comprises

a metal oxide semiconductor circuit having a first pass-through switching element for connecting said data ready input signal line to said data ready output line, and

a digital circuit means for latching said pass-through switching element to connect said data ready input and output lines when said buffer available line indicates the availability of data in said associated buffer at a time after said data ready input line signal level indicates that no data is available, and for latching said pass-through switching element for isolating said data ready input line from said data ready output line when said buffer available line has a signal thereon indicating the absence of available data in said associated buffer memory.

6. The data buffer allocation array circuit of claim 5 wherein said pass-through switching element is a metal oxide semiconductor bidirectional switching device.

7. The data buffer allocation array circuit of claim 5 further wherein said buffer line setting means comprises

a latching circuit for setting said buffer available line to a state wherein said line provides a signal indicating the absence of data in response to a clear signal on said clear line,

said latching circuit being responsive to a signal on said data ready input line, indicating the presence of data, for setting said buffer available line to a state indicating the presence of data in said associated buffer, said buffer available line indicating the absence of data thereafter only in resposne to a clear signal, and

wherein said digital circuit is responsive to the termination of the data available signal on said data ready input line at a time after said buffer available line indicates the presence of data in said associated buffer, for setting said pass-through device to said connection state wherein said data ready input line and data ready output lines are connected, and

said digital circuit is further responsive to the change of signal level on the said buffer available line indicating the absence of data for causing said pass-through device to isolate said data available input and output lines.

8. A data buffer array allocation circuit for directing incoming data to an available one of a plurality of buffer memories, said circuit comprising

a plurality of buffer selection circuits, each circuit being associated with one of said buffer memories and having

a clear input line,

a data ready input line,

a data ready output line, and

a buffer available line,

means for connecting said selection circuits in an ordered linear array, the data ready output line of an earlier buffer selection circuit of the linear array being connected to the data ready input line of a next succeeding buffer selection circuit,

means for directing said incoming data into the one of said plurality of buffer memories which is associated with the first buffer selection circuit of the ordered array wherein the data ready input and data ready output lines are effectively isolated from each other,

each said buffer selection circuit further comprising

a metal oxide semiconductor circuit having a controllable pass-through switching element for connecting said data ready input line to said data ready output line,

a first latching circuit for setting said buffer available line in response to a clear signal on said clear line to a state wherein said line provides a signal indicating the absence of data in the associated buffer memory,

said latching circuit being responsive to a signal on said data ready input line, indicating the presence of data, for setting said buffer available line to a state indicating the presence of data in said associated buffer, and to reset said buffer available line to indicate the absence of data thereafter only in response to a clear signal,

a second latching circuit

for controlling said pass-through switching element for effectively connecting said data ready input line to the data ready output line at a time after said buffer available line indicates the availability of data in said associated buffer and the data ready input line signal level indicates that no data is available, and

for latching said pass-through switching element for isolating said data ready input line from said data ready output line when said buffer available line has a signal thereon indicating the absence of available data in said associated buffer memory,

said second latching circuit being further responsive to the change of signal level on said buffer available line to a signal indicating the absence of data, for causing said pass-through switching element to effectively isolate the data ready input and data ready output lines, and

wherein said second latching circuit is further responsive to the termination of the data available signal on said data ready input line at a time after said buffer available line indicates the presence of data in said associated buffer for controlling the pass-through device to connect said data ready input line and said data ready output line, and

a line pull-up circuit for providing a signal on said data ready input line indicating the absence of ready data when said data ready input line is effectively otherwise in a floating condition.