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Programmable logic array, including an arrangement for invalidating faulty and term outputs

  • US 4,511,812 A
  • Filed: 06/15/1982
  • Issued: 04/16/1985
  • Est. Priority Date: 06/24/1981
  • Status: Expired due to Fees
First Claim
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1. A programmable logic array comprising:

  • an AND array having a plurality of first input lines and a plurality of first output lines as AND terms, said AND array being programmed by electrically connecting selected ones of said first input lines and selected ones of said first output lines;

    an OR array having a plurality of second input lines connected to corresponding ones of said first output lines and a plurality of second output lines, said OR array being programmed by electrically connecting selected ones of said second input lines and selected ones of said second output lines; and

    invalidating means for selectively connecting said first output lines forming said AND terms or said second input lines to a constant potential source.

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