Programmable logic array, including an arrangement for invalidating faulty and term outputs

• US 4,511,812 A
• Filed: 06/15/1982
• Issued: 04/16/1985
• Est. Priority Date: 06/24/1981
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Satake, Shozo
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US06/388,620
• Time in Patent Office: 1,036 Days
• Field of Search: 307/465, 307/466, 307/467, 307/468, 307/469, 307/442, 307/443, 307/445, 307/242, 307/557, 307/558, 307/559, 307/562, 307/563, 364/716, 371/10, 371/11, 340/825.83, 365/96, 365/103, 365/104, 365/200, 365/201
• US Class Current: 326/14
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: H03K 19/17708 using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Abstract

A programmable logic array comprises an AND array for producing AND term outputs on a plurality of AND term lines, an OR array which receives the AND term output of the AND array as inputs thereto, and an AND term disregarding array connected to the AND term lines to selectively invalidate the AND term outputs. The AND term disregarding array functions to disregard one of the AND terms on which a program defect is present.

Claims

1. A programmable logic array comprising:

an AND array having a plurality of first input lines and a plurality of first output lines as AND terms, said AND array being programmed by electrically connecting selected ones of said first input lines and selected ones of said first output lines;

an OR array having a plurality of second input lines connected to corresponding ones of said first output lines and a plurality of second output lines, said OR array being programmed by electrically connecting selected ones of said second input lines and selected ones of said second output lines; and

invalidating means for selectively connecting said first output lines forming said AND terms or said second input lines to a constant potential source.

2. A programmable logic array according to claim 1, wherein said invalidating means includes a line connected to said constant potential source, and means for connecting said first output lines or said second input lines to said line.

3. A programmable logic array according to claim 1 wherein said invalidating means includes a plurality of third input lines connected to corresponding ones of said first output lines forming said AND terms or said second input lines and a line connected to a constant potential source, said invalidating means electrically connecting one of said third input lines corresponding to one of said AND terms to be disregarded to said line connected to said constant potential source.

4. A programmable logic array comprising:

an AND array for producing AND term outputs on a plurality of AND term lines;

an OR array connected to said AND term lines to receive said AND term outputs of said AND array as inputs thereto; and

invalidating means for selectively connecting said AND term lines to a constant potential source.

5. A programmable logic array according to claim 4 wherein said invalidating means includes a line connected to a constant potential source, said invalidating means for electrically connecting one of said AND term lines corresponding to one of said AND terms to be disregarded to said constant potential source.