Synchronous AM demodulator with quadrature signal cancellation

• US 4,511,848 A
• Filed: 06/15/1983
• Issued: 04/16/1985
• Est. Priority Date: 06/15/1983
• Status: Expired due to Term

• Current Assignee: Watson Industries, Inc.
• Original Assignee: Watson Industries, Inc.
• Inventors: Watson, William S.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US06/504,585
• Time in Patent Office: 671 Days
• Field of Search: 329/50, 329/145, 329/166, 329/168, 329/169
• US Class Current: 329/349
• CPC Class Codes: H03D 1/2245 using two quadrature channels H03D1/2209 takes precedence

Abstract

A method and apparatus for removing quadrature error signal components from synchronous AM demodulation signals are disclosed. A synchronous AM demodulator processes a synchronous sensor output signal in phase relation to a phase reference signal. Means are provided for dynamically producing a counteracting signal that is stably phase related to the system reference signal. The counteracting signal is in phase with the quadrature component of the synchronous signal such that when added to the synchronous signal, the quadrature component thereof is minimized or eliminated.

Claims

1. A method of removing a quadrature error signal component from a synchronous signal in a synchronous AM demodulator network having a phase reference signal, comprising the steps of:

(a) generating a counteracting signal, phase related in stable manner to the system phase reference signal; and

(b) mixing said counteracting signal with said synchronous signal, wherein said counteracting signal subtracts from the quadrature error signal component of said synchronous signal.

2. The method of claim 1, including the step of controlling the amplitude of said counteracting signal mixed with said synchronous signal by a closed feedback circuit that dynamically adjusts to changing circuit and environmental parameters.

3. The method as recited in claim 2, wherein said amplitude controlling step further comprises:

(a) sampling the synchronous signal in 180 degrees sample segments;

(b) accumulating the average of said samples as a bias voltage in an integrator;

wherein the output slew rate of said integrator is proportional to the average sample error; and

(c) summing said accumulated bias voltage in phase relation to the system phase reference signal, with said synchronous signal, to close the control loop.

4. The method of claim 1, wherein the step of generating the counteracting signal in phase relation to the system phase reference signal comprises the steps of:

integrating said system phase reference signal; and

dynamically controlling the bias level of said integrated system phase reference signal by a closed feedback loop.

5. In combination with a synchronous AM demodulator circuit of the type suitable for demodulating a synchronous signal having a quadrature component, circuit means operatively connected with said demodulator circuit for dynamically minimizing said quadrature component of said synchronous signal.

6. A quadrature corrector demodulator circuit comprising:

(a) synchronous AM demodulator circuit means operatively connected to receive a synchronous input signal and a synchronous phase reference input signal, for providing a demodulated output signal responsive thereto;

said synchronous signal including a quadrature signal component;

(b) counteracting signal producing circuit means operatively connected to receive said synchronous input signal and said phase reference input signal for dynamically generating in response thereto a counteracting signal that is stable and phase related to said synchronous phase reference signal; and

(c) mixing circuit means operatively connected to receive said synchronous input signal and said counteracting signal for summing said signals;

wherein said counteracting signal tends to cancel said quadrature signal component of said synchronous signal.

7. A quadrature corrector demodulator circuit as recited in claim 6, wherein said counteracting signal producing circuit means includes integrator circuit means operatively connected for integrating said phase reference input signal to produce a quadrature phase reference signal that is 90 degrees out of phase from the synchronous phase reference signal.

8. A quadrature corrector demodulator circuit as recited in claim 7, wherein said counteracting signal producing circuit means further includes feedback circuit means operatively connected with said integrator circuit means for providing a closed loop bias control for said quadrature phase reference signal.

9. A quadrature corrector demodulator circuit as recited in claim 7, wherein said counteracting signal producing circuit means further includes sampling circuit means operatively connected to receive said synchronous input signal and said quadrature phase reference signal for producing a sampled signal in response to said quadrature phase reference signal, characterized by 180 degree polarized sample segments of said synchronous input signal.

10. A quadrature corrector demodulator circuit as recited in claim 9, wherein said counteracting signal producing circuit means further includes circuit means for averaging and accumulating said sampled signals to produce an output slew rate bias signal proportional to said accumulated average signal.

11. A quadrature corrector demodulator circuit as recited in claim 10, wherein said averaging and said accumulating circuit means comprises an integrator network.

12. A quadrature corrector demodulator circuit as recited in claim 10, wherein said counteracting signal producing circuit means further includes multiplier circuit means operatively connected for receiving and multiplying said slew rate bias signal and said quadrature phase reference signals, to produce said counteracting signal;

wherein said sampling circuit means, said averaging and accumulating circuit means, said multiplier circuit means and said mixing circuit means form a closed-loop feedback system.

13. A quadrature corrector demodulator circuit as recited in claim 9, wherein said sampling circuit means comprises a digital bilateral switching circuit.

14. A vibratory element sensor apparatus comprising:

(a) a vibratory element sensor of the type that produces a sensed synchronous output signal in response to an impressed force;

(b) drive means for driving said sensor with a phase reference signal;

(c) synchronous AM demodulator circuit means operatively connected to receive said sensed synchronous output signal and said phase reference signal, for producing a demodulated output signal responsive thereto, said sensed synchronous output signal including a quadrature signal component;

(d) counteracting signal producing circuit means operatively connected to receive said sensed synchronous output signal and said phase reference signal for dynamically generating in response thereto a counteracting signal that is phase related, in stable manner, to said phase reference signal; and

(e) mixing circuit means operatively connected to receive said sensed synchronous output signal and said counteracting signal for summing the two signals;

wherein said counteracting signal tends to cancel said quadrature signal component of said sensed synchronous output signal.

15. A vibratory element sensor apparatus as recited in claim 14, wherein said vibratory element sensor comprises a piezoelectric crystal.