Dual signal electromagnetic article theft detector

• US 4,511,888 A
• Filed: 06/29/1983
• Issued: 04/16/1985
• Est. Priority Date: 06/29/1983
• Status: Expired due to Term

• Current Assignee: 3SI Security Systems, Inc. (3SI Holdco, Inc.)
• Original Assignee: U.S. Currency Protection Corp. (3SI Holdco, Inc.)
• Inventors: Bernhardt, Terry L.
• Primary Examiner(s): Swann, III, Glen R.
• Application Number:
  US06/509,288
• Time in Patent Office: 657 Days
• Field of Search: 340/568, 340/571, 340/572
• US Class Current: 340/571
• CPC Class Codes: G08B 13/2431 Tag circuit details
• CPC Class Codes: G08B 13/2474 Antenna or antenna activator geometry, arrangement or layout loop antennae H01Q1/22
• CPC Class Codes: G08B 13/2477 Antenna or antenna activator circuit
• CPC Class Codes: G08B 13/2482 EAS methods, e.g. description of flow chart of the detection procedure
• CPC Class Codes: G08B 13/2488 Timing issues, e.g. synchronising measures to avoid signal collision, with multiple emitters or a single emitter and receiver
• CPC Class Codes: G08B 15/02 with smoke, gas, or coloured or odorous powder or liquid

Abstract

A transmitter emits a pulsed radio signal and a digitally encoded radio signal near each exit of a protected premises. Monitored articles carry a receiver having a first circuit for receiving the pulsed signal, a power source, and a power switch for coupling the power source to a second circuit on detection of the pulsed signal. The second circuit receives the digitally encoded signal as multiple, serially-transmitted code bits. It also contains a clock for generating timing signals synchronized by the pulsed signal in order to distinguish a plurality of code bit intervals. A processor, an associated memory, and an address counter compare the digitally encoded signal with a stored bit pattern. On receiving an improper code bit, the processor causes the power switch to decouple the power source from the second circuit to conserve power. If the received signal matches the stored bit pattern, power is maintained to the second circuit. Alarm circuitry is triggered by overflow from the address counter. The address counter is reset each time the pulsed signal is received and thus produces no overflow, but when the article is removed from the protected premises, the address counter is allowed to overflow triggering the alarm circuit.

Claims

1. A security system for detecting the removal of an article from a premises to be protected, the protected premises including at least one exit through which the article may be removed from the protected premises, said security system comprising in combination:

a. a transmitter for transmitting first and second signals in the vicinity of said exit, said first signal being transmitted as a series of periodic pulses having a first predetermined period of time therebetween;

b. receiver means carried by said article, said receiver means including;

i. an electrical power source;

ii. a first receiver for detecting the presence of said first signal, said first receiver being continuously coupled to said electrical power source for continuously receiving electrical power therefrom, said first receiver generating an enabling signal upon detecting said first signal;

iii. a second receiver for detecting the presence of said second signal and providing an alarm in response thereto, said second receiver generating a disabling signal upon failing to detect said second signal within a second predetermined period of time after said enabling signal is generated, said second predetermined period of time being shorter than said first predetermined period of time; and

iv. power switching means responsive to said enabling and disabling signals for selectively electrically coupling said electrical power source to said second receiver following the generation of said enabling signal and decoupling said electrical power source from said second receiver means following the generation of said disabling signal for lessening the amount of electrical power drained from said electrical power source during instances when said receiver means is exposed to said first signal in the absence of said second signal.

2. A security system as recited by claim 1 wherein said first and second signals are transmitted as electromagnetic radio waves of first and second frequencies, respectively, and wherein said first receiver includes a first filter for passing signals of said first frequency and said second receiver means includes a second filter for passing signals of said second frequency.

3. A security system as recited by claim 2 wherein said first filter is an active filter comprising:

a. a first current programmable operational amplifier having an inverting input terminal and an output terminal and including a first feedback resistor of a first magnitude coupled therebetween;

b. a second current programmable operational amplifier having an inverting input terminal coupled to the output of said first operational amplifier, said second operational amplifier having an output terminal;

c. a second feedback resistor coupled between the output terminal of said second operational amplifier and the inverting input terminal of said first operational amplifier, the ratio of the magnitude of the first feedback resistor to the magnitude of the second feedback resistor being greater than unity to increase the selectivity of said first filter; and

d. said first and second operational amplifiers are programmed to operate at substantially minimum current levels to minimize power drawn from said electrical power source and to minimize the bandwidth of the gain provided by each of said first and second operational amplifiers to increase the selectivity of said first filter and to decrease the tendency of said first filter to oscillate.

4. A security system as recited by claim 1 wherein said power switch means includes a clocked data latch having a forced-state input, a clock input, a data input, and an output, said clocked data latch being coupled to said electrical power source for being continuously powered thereby, said power switch means also including a transistor having a control terminal coupled to the output of said clocked data latch for switching said transistor between conductive and non-conductive states, said transistor including two additional terminals coupled to said electrical power source and to said second receiver, respectively, for electrically coupling said electrical power source to said second receiver when said transistor is switched to its conductive state, said forced-state input of said clocked data latch receiving said enabling signal for forcing the output of said clocked data latch to a first state that renders said transistor conductive.

5. A security system as recited by claim 4 wherein said second receiver, after being electrically coupled to said electrical power source, generates at least one clocking signal a predetermined time after said enabling signal is generated, said second receiver means also generating at least one data signal representative of whether said second signal has been detected, and wherein said clocking signal and said data signal are provided to said clock input and to said data input of said clocked data latch, respectively, for causing the output of said clocked data latch to assume a state determined by said data signal when said clocking signal is generated and thereby control the conduction of said transistor.

6. A security system as recited by claim 4 wherein said second signal is transmitted as a plurality of serially coded bits following transmission of each periodic pulse of said first signal, said serially coded bits being transmitted by said transmitter during a corresponding plurality of successive code bit intervals, said second receiver being adapted to receive said serially coded bits when said receiver means is brought into the vicinity of said exit, and wherein said second receiver includes processing means for providing a clocking signal to the clock input of said clocked data latch to distinguish each of said plurality of code bit intervals, said processing means storing a pattern of code bits and comparing the serially coded bit received during each code bit interval with a corresponding stored code bit to determine whether they match one another, said processing means providing a data signal to the data input and said clocked data latch for each code bit interval, said data signal being representative of whether, for a particular code bit interval, the serially coded received bit matched the corresponding stored code bit, said clocking signal and said data signal causing the output of said clocked data latch to assume a state determined by the status of said data signal when the clocking signal is generated and thereby decoupling said second receiver from said electrical power source substantially immediately after the occurrence of a code bit interval in which the serially coded received bit does not match the corresponding stored code bit.

7. A security system as recited by claim 6 wherein said first and second signals are transmitted as electromagnetic radio waves of first and second frequencies and wherein said first receiver includes a filter for passing signals of said first frequency and said second receiver includes a filter for passing signals of said second frequency.

8. A security system as recited by claim 7 wherein said second receiver includes synchronizing means responsive to said enabling signal for generating timing signals provided to said processing means, said processing means being responsive to said timing signals to distinguish between each of said plurality of successive code bit intervals.

9. A security system as recited by claim 8 wherein said synchronizing means includes:

a. a master clock for generating a periodic master clock signal having a frequency greater than the first frequency of said first signal;

b. a synch-pulse generator having a clock terminal for receiving said master clock signal, an output terminal for providing a synch-pulse, and a forced-state terminal coupled to said first receiver and responsive to said enabling signal, said synch-pulse generator causing said output terminal to assume a first state upon initial receipt of said enabling signal and causing said output terminal to assume a second state upon the receipt of the master clock signal next following the initial receipt of said enabling signal; and

c. timing means coupled to said master clock for receiving said master clock signal and coupled to the output terminal of said synch-pulse generator and responsive to a change in the state thereof for timing the generation of said timing signals provided to said processing means.

10. A security system as recited by claim 9 wherein said master clock is a crystal oscillator.

11. A security system as recited by claim 9 wherein said synch-pulse generator includes:

a. a first clocked flip-flop having a clock input, a data input, a forced-state input and an output, the data input of said first clocked flip-flop being coupled to a source of a logic level tending to cause the output of said first clocked flip-flop to assume a first state when first clocked flip-flop is clocked, the forced-state input of said first clocked flip-flop being coupled to said forced-state terminal of said synch-pulse generator and causing the output of said first clocked flip-flop to assume a second state in response to the initial receipt of said enabling signal;

b. a second clocked flip-flop having a clock input, a data input, a forced-state input and an output, the data input of said second clocked flip-flop being coupled to the output of said first clocked flip-flop, the forced state input of said second clocked flip-flop being coupled to said forced-state terminal of said synch-pulse generator and causing the output of said second clocked flip-flop to assume a first state in response to the initial receipt of said enabling signal;

c. the clock inputs of each of said first and second clocked flip-flops being coupled to the clock terminal of said synch-pulse generator for receiving said master clock signal;

d. the output of said second clocked flip-flop assuming a second state opposite to the first state thereof upon receiving a master clock signal next following the occurrence of the initial receipt of said enabling signal, the output of said second clocked flip-flop returning to the first state thereof upon receipt of a second master clock signal next following the occurrence of the initial receipt of said enabling signal; and

e. the output of said second clocked flip-flop being coupled to the output terminal of said synch-pulse generator for providing a pulse having a width equal to one period of the master clock following the initial receipt of said enabling signal.

12. A security system as recited by claim 7 wherein said processing means includes:

a. a microprocessor having a plurality of instruction input terminals for receiving a multiple-bit instruction code representative of an operation to be performed by said microprocessor, said microprocessor further including at least one bi-directional data port for receiving data and transmitting data and including a clock terminal for receiving a first timing signal to synchronize the performance of operations within said microprocessor and to synchronize the receipt of data by and the transmission of data from said microprocessor;

b. an addressable memory having a plurality of address input terminals for receiving an address and having a plurality of output terminals at least some of which are coupled to the instruction input terminals of said microprocessor for providing an instruction code thereto;

c. an address counter having a clock terminal for receiving a second timing signal, said address counter having a plurality of output terminals at least some of which are coupled to the address input terminals of said addressable memory for providing an address thereto, said address counter causing the address provided by the output terminals thereof to be sequentially modified each time said second timing signal is received by the clock terminal of said address counter;

d. timing means for generating said first and second timing signals; and

e. coupling means for selectively coupling said second filter to the bi-directional data port of said microprocessor during each code bit interval for allowing said microprocessor to compare the serially coded bit received during a particular code bit interval to a corresponding stored code bit.

13. A security system as recited by claim 12 wherein:

a. said microprocessor includes a pulse output terminal for generating a pulse upon receiving a first instruction code at its instruction input terminals;

b. said addressable memory is programmed to provide said first instruction code during each of the plurality of code bit intervals; and

c. said pulse output terminal is coupled to the clock input of said clocked data latch for providing said clocking signal thereto for each code bit interval.

14. A security system as recited by claim 13 wherein said microprocessor also includes a write output for signaling the operation of writing data on the bi-directional data port and wherein said processing means further includes a clocked flip-flop having an output and having a data input, said data input of said clocked flip-flop being coupled to the bi-directional data port of said microprocessor, said clocked flip-flop also having a clock input coupled to the write output of said microprocessor for clocking data presented to the data input thereof to the output thereof, the output of said clocked flip-flop being coupled to the data input of said clocked data latch for providing said data signal thereto.

15. A security system as recited by claim 14 wherein:

a. said microprocessor includes a further output terminal for generating a further signal upon receiving a second instruction code at its instruction input terminals;

b. said addressable memory is programmed to provide said second instruction code after receiving all of the plurality of serially coded bits transmitted by said transmitter;

c. said processing means includes a correct code latch circuit having a trigger input coupled to said further output terminal of said microprocessor, said correct code latch also including an output which changes its state when said further signal is received at the trigger input thereof; and

d. said clocked flip-flop includes a forced-state input coupled to the output of said correct code latch circuit, said forced-state input causing the output of said clocked flip-flop to permanently assume a state which, when coupled to the data input of said clocked data latch and clocked therein, causes said transistor of said power switch means to remain conductive.

16. A security system as recited by claim 12 wherein said address counter is incremented by said second timing signal and wherein said address counter includes a reset input terminal for initializing the address provided by the output terminals thereof, said address counter further including a high-order output terminal for providing a trigger signal when said address counter is incremented to a predetermined number, said predetermined number being greater than the number of times said second timing signal is received by the clock terminal of said address counter within said first predetermined period between pulses of said first signal, said security system further including reset circuitry for applying a reset pulse to the reset input terminal of said address counter each said first signal is detected by said first receiver to initialize the output terminals of said address counter, said reset pulse preventing said trigger signal from occurring so long as said first signal is detected by said first receiver and thereby holding off the triggering of the alarm until said receiver is removed from the vicinity of said exit.

17. A security system as recited by claim 12 wherein:

(a) said addressable memory includes a data terminal for providing data representative of stored code bits therein, said addressable memory including at least one selector output terminal for providing a selector signal; and

(b) said coupling means includes a first input terminal coupled to the data terminal of said addressable memory for receiving the stored code bits, a second input terminal coupled to said filter for receiving the serially coded bit received during a particular code bit interval, a third input terminal for receiving said selector signal, and an output terminal coupled to the bidirectional data port of said microprocessor for selectively coupling the stored code bits and the received serially coded bits to said microprocessor.

18. A security system as recited by claim 7 wherein said transmitter includes:

(a) clocking means for generating first and second clocking signals of said first and second frequencies, said clocking means also generating a third clocking signal having a period equal to the duration of one of said code bit intervals;

(b) a counter responsive to said third clocking signal for providing a periodically incremented code address;

(c) pattern generator means responsive to said periodically incremented code address for providing first and second gating signals, said second gating signal incorporating the serially coded bit pattern to be transmitted by said second signal;

(d) gating means having first and second inputs for receiving said first and second clocking signals, respectively, and having third and fourth inputs for receiving said first and second gating signals, respectively, and having a summing output, said gating means selectively coupling said first clocking signal to said summing output under the control of said first gating signal and selectively coupling said second clocking signal to said summing output under the control of said second gating signal, said summing output providing a summed output signal;

(e) an amplifier coupled to said summing output for amplifying the summed output signal and providing an amplified signal; and

(f) means coupled to said amplifier and responsive to said amplified signal for radiating said first and second electromagnetic radio waves.

19. A security system as recited by claim 18 wherein:

(a) the summing output of said gating means provides the summed output signal as a voltage which switches between first and second nonnegative voltage levels relative to ground potential;

(b) said security system includes level translation means coupled to said amplifier for shifting the summed output signal to a bipolar signal switching between positive and negative voltage levels relative to ground potential; and

(c) said security system further includes zero level control means responsive to said first and second gating signals for selectively causing the input of said amplifier to assume a voltage substantially equal to ground potential whenever both said first and second gating signals decouple said first and second clocking signals, respectively, from said summing output, in order to minimize power consumed by said amplifier when neither the first nor the second clocking signals are coupled to said amplifier.

20. A security system as recited by claim 19 wherein:

(a) said amplifier includes an operational amplifier having inverting and non-inverting input terminals and an output terminal, said non-inverting terminal being coupled to a source of ground potential and said inverting terminal being coupled by a feedback network to the output terminal thereof;

(b) said gating means including a first resistor coupled between the summing output thereof and the inverting terminal of said operational amplifier for providing the summed output signal;

(c) said level translation means comprises a current sink for withdrawing current of a predetermined magnitude from the inverting terminal of said operational amplifier; and

(d) said zero level control means comprises a switchable current source responsive to said first and second gating signals for sourcing a current to the inverting terminal of said operational amplifier, the sourced current being of a first magnitude approximately equal to said predetermined magnitude for substantially inhibiting said level translation means when neither the first nor the second clocking signals are coupled to said amplifier, the sourced current being switched to a second magnitude when either of said first or second gating signals couples said first or second clocking signals to said amplifier, said second magnitude being substantially smaller than said first magnitude.