Digital signal processing system

• US 4,511,966 A
• Filed: 01/28/1983
• Issued: 04/16/1985
• Est. Priority Date: 02/19/1982
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Hamada, Osamu
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/462,049
• Time in Patent Office: 809 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 708/490
• CPC Class Codes: G06F 9/24 Loading of the microprogram
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

Described is a digital signal processor including at least two memories, that is, a microprogram memory for storing a series of microinstructions for instructing a digital signal processing procedure, and a coefficient memory for storing coefficient data required for performing a series of arithmetic operations on the digital signal data. These data being transferred and written into said microprogram memory and said coefficient memory from a host computer system. The coefficient memory has at least two pages corresponding to the total memory area which may be addressed during digital signal processing to be effected by said microinstructions. Page selection of the coefficient memory may be performed from said host computer system.

Claims

1. A digital signal processing system comprising

microprogram memory means for storing a plurality of microinstructions for instructing a digital signal processing procedure,

coefficient memory means for storing coefficient data required for performing a series of arithmetic operations on digital signal data,

a host computer system,

means for writing data into said microprogram memory means and said coefficient memory means from said host computer system,

said coefficient memory means having at least two selectable pages corresponding to a total memory area accessible during digital signal processing in accordance with said microinstructions, and

said host computer system controlling page selection of said pages of said coefficient memory means.

2. The digital signal processing system according to claim 1 further including

means for reading said microinstructions sequentially from said microprogram memory means,

said coefficient data being double precision data, with upper and lower single word halves,

means for reading said double precision coefficient data from said coefficient memory means,

multiplier means for multiplying said digital signal data by said double precision coefficient data read from said coefficient memory means,

said multiplier means including means for producing a first double precision product output representing a product of said upper half of said double precision coefficient data and said digital signal data and for producing a second double precision output representing a second product of said lower half of said double precision coefficient data and said digital signal data,

means for shifting said second output by bits equivalent to one word, and

means for summing said first output and said shifted second output to effect multiplication of said digital signal data by said double precision coefficient data.

3. A digital signal processing system comprising

a digital signal processing unit including microprogram memory means for storing a plurality of microinstructions for instructing a digital signal processing procedure, and coefficient memory means for storing coefficient data required for performing a series of arithmetic operations on digital signal data,

memory control means,

at least one memory block for storing said digital signal data,

a host computer system,

means for writing data into said microprogram memory means and said coefficient memory means from said host computer system,

said coefficient memory means having at least two selectable pages corresponding to a total memory area accessible during digital signal processing in accordance with said microinstructions,

said host computer system controlling page selection of said pages of said coefficient memory means,

said memory control means including address management memory means for dividing said at least one memory block into a plurality of memory cells identified by respective boundary addresses,

means for writing said boundary addresses of said memory cells from said host computer system into said address management memory means,

said memory cells being accessible in accordance with serial memory cell numbers designated from said digital signal processing unit.