Overvoltage protection circuit for power supply

• US 4,513,341 A
• Filed: 07/25/1983
• Issued: 04/23/1985
• Est. Priority Date: 07/25/1983
• Status: Expired due to Fees

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: GTE Lenkurt Incorporated (Verizon Communications Inc.)
• Inventors: Kollanyi, Miklos J.
• Primary Examiner(s): Salce, Patrick R.
• Application Number:
  US06/516,503
• Time in Patent Office: 638 Days
• Field of Search: 361/18, 361/91, 361/88, 361/89, 361/94, 361/59, 361/58, 307/135, 307/141, 307/141.4, 307/125, 307/131
• US Class Current: 361/91.3
• CPC Class Codes: H02H 3/202 for dc systems
• CPC Class Codes: H02H 9/004 in connection with live-insertion of plug-in units involving communication with a central processing unit G06F13/40

Abstract

Surge-current that occurs when the pair of input lines of a power supply are energized is limited by connecting the source-to-drain path of an insulated gate FET in series in one input line and connecting its gate to an intermediate node of a voltage divider that is connected across the input lines, with an integrating capacitor connected between the node and one input line for reducing the rate of conduction of the FET. Overvoltage protection is provided by electrically connecting a latch circuit between the node and the one input line, with the FET'"'"'s gate being electrically connected to the collector of a latch transistor that has its base driven by an overvoltage indication. The series combination of a timing resistor and timing capacitor is connected across the primary conduction path of the FET and the base of a unijunction transistor that has its emitter directly connected to the junction of the resistor and capacitor and AC coupled to the base of the latch transistor. A prescribed time interval (set by charging the timing capacitor to the trigger voltage of the unijunction) after the latch is set by an overvoltage condition, the unijunction fires for discharging the timing capacitor and resetting the latch, and thus the power supply.

Claims

1. Apparatus responsive to an overvoltage indication from an overvoltage sensing circuit of a power supply for interrupting electrical connection of a pair of input lines that are connected between the power supply and a power source, comprising:

first means having a primary conduction path thereof electrically connected in series in one of the power supply input lines, said first means conducting substantial current in said primary conduction path in said one line in response to a prescribed control voltage of greater than a prescribed value applied to a control lead thereof;

second means electrically connected across the input lines for developing said control voltage of greater than the prescribed value at a node therebetween when the input lines are connected to the power source;

third means for electrically connecting said node to the control lead of said first means for causing the latter to conduct current through the power supply when the control voltage is greater than the prescribed value; and

latch means electrically connected between said node and said one input line and having an input terminal connected to the overvoltage sensing circuit, said latch means being responsive to an overvoltage signal from said sensing circuit on said input terminal for decreasing the value of control voltage to much less than the prescribed value for cutting off said first means for causing said first means to block current flow in said one input line.

2. Apparatus according to claim 1 wherein said second means comprises a voltage divider electrically connected between the two input lines and having said node between resistors thereof, said latch means being responsive to an overvoltage signal for decreasing the resistance between said node and said one input line for decreasing the control voltage to much less than the prescribed value for cutting off said first means.

3. Apparatus according to claim 2 further comprising fourth means electrically connected between said node and said one input line for limiting the rate of increase of said control voltage at said node when the input lines are initially connected to the power source and thereby limiting the conduction rate of said first means and the rate of current increase in the lines.

4. Apparatus according to claim 3 wherein said fourth means comprises an integrating capacitor.

5. Apparatus according to claim 4 wherein said first means comprises a field effect transistor having a conduction characteristic with a soft knee whereby its conduction rate gradually increases with increase in gate-control voltage until the latter reaches a threshold value, which is the prescribed value, above which its primary conduction path approaches a much lower resistance.

6. Apparatus according to claim 5 wherein said first means is an insulated gate field effect transistor.

7. Apparatus according to claim 2 comprising fourth means electrically connected between said input terminal of said latch means and said one input line for bypassing high frequency components in the output of the overvoltage sensing circuit.

8. Apparatus according to claim 2 wherein said latch means comprises first and second transistors of opposite conductivity types each having a base electrode and each having its primary, i.e., emitter-collector, conduction path and collector resistors electrically connected in series between said node and said one input line in a separate branch, and each latch transistor having its base electrode electrically connected to a node between collector resistors of the other transistor;

and fourth means electrically connecting the overvoltage signal to the base electrode of one of said first and second transistors.

9. Apparatus according to claim 8 wherein the collector electrode of one of said latch transistors is electrically connected to said control lead.

10. Apparatus responsive to an overvoltage indication from an overvoltage sensing circuit of a power supply for interrupting electrical connection of a pair of input lines that are connected between the power supply and a power source, comprising:

first means having a primary conduction path thereof electrically connected in series in one of the power supply input lines, said first means conducting substantial current in said primary conduction path in said one line in response to a prescribed control voltage of greater than a prescribed value applied to a control lead thereof;

second means electrically connected across the input lines for developing said control voltage of greater than the prescribed value at a node therebetween when the input lines are connected to the power source;

said second means comprising a voltage divider electrically connected between the two input lines and having said node between resistors thereof;

third means for electrically connecting said node to the control lead of said first means for causing the latter to conduct current through the power supply when the control voltage is greater than the prescribed value;

latch means comprising an input terminal connected to the overvoltage sensing circuit, and first and second transistors of opposite conductivity types each having a base electrode and each having its primary, i.e., emitter-collector, conduction path and collector resistors electrically connected in series between said node and said one input line in a separate branch;

each of said latch transistors having its base electrode electrically connected to a node between collector resistors of the other latch transistor;

fourth means electrically connecting the overvoltage signal to the base electrode of one of said first and second transistors;

said third means resistively electrically connecting said node to said control lead of said first means through a collector resistor of one of said first and second transistors;

said latch means being responsive to an overvoltage signal from said sensing circuit on said input terminal thereto for decreasing the value of control voltage to much less than the prescribed value for cutting off said first means for causing said first means to block current flow in said one input line.

11. Apparatus according to claim 10 including means for resetting said latch means at a prescribed time interval after it is set.

12. Apparatus according to claim 11 wherein said reset means comprises:

a first timing resistor and a first timing capacitor electrically connected in series across the primary conduction path of said first means;

fifth means AC coupling the junction of said first resistor and first capacitor to the base electrode of one of said first and second transistors; and

sixth means, which is a voltage breakdown means, electrically connected across the said first capacitor;

said first capacitor charging when said first means is cut off by said latch means;

said first capacitor discharging through said sixth means when the charge voltage on the former exceeds a prescribed threshold level whereby said fifth means couples a representation of discharge of said first capacitor to the base electrode of one of said first and second transistors for resetting said latch circuit.

13. Apparatus according to claim 12 wherein one sides of said first resistor and first capacitor are electrically connected together and said voltage breakdown means comprises a unijunction transistor having first and second base electrodes connected to other sides of said first resistor and capacitor and an emitter electrode connected to the junction of said one sides of said first resistor and first capacitor.

14. Apparatus according to claim 13 further comprising a second AC coupling capacitor electrically connected between the base electrodes of said unijunction transistor for bypassing AC components on the input lines.

15. Apparatus according to claim 14 wherein said first means comprises an insulated gate field effect transistor.