Apparatus and method for suppressing side lobe response in a digitally sampled system

• US 4,513,385 A
• Filed: 01/31/1983
• Issued: 04/23/1985
• Est. Priority Date: 01/31/1983
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Muri, David L.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Huang, Karl
• Application Number:
  US06/462,494
• Time in Patent Office: 813 Days
• Field of Search: 364/572, 364/574, 364/724, 364/726, 343/379, 333/166, 367/905
• US Class Current: 702/74
• CPC Class Codes: H01Q 3/2605 Array of radiating elements provided with a feedback control over the element weights, e.g. adaptive arrays
• CPC Class Codes: Y10S 367/905 Side lobe reduction or shading

Abstract

A decoder circuit is provided which employs digital sampling and correlation apparatus to detect the presence of a received tone signal exhibiting a predetermined frequency. Samples of received tone signals are taken and, in effect, multiplied by a substantially rectangular observation window which includes a bite interval of selected duration and location therein. A correlator correlates the windowed samples to detect samples corresponding to the predetermined frequency (main lobe frequency). A significant decrease in undesired side lobe response is thus achieved.

Claims

1. A decoder circuit for detecting the presence of a signal exhibiting a predetermined frequency, comprising:

timing means for generating observation interval signals;

sampling means, responsive to said timing means, for sampling a first signal to produce samples thereof including a first sample during a substantially rectangular observation interval, said sampling means including means for ignoring a portion of said samples occurring near the beginning of said observation interal and after said first sample, and

correlation means, electrical coupled to said sampling means, for correlating said samples with a predetermined pattern to detect the presence of a signal exhibiting said predetermined frequency within said first signal.

2. The circuit of claim 1 wherein said means for ignoring further includes means for dropping a plurality of successive samples within a bite interval occurring in a portion of said observation interval, said bite interval having its center located between approximately 0.02 T1 and 0.28 T1, wherein T1 is defined to be the time duration of the observation interval.

3. The circuit of claim 1 including means, responsive to said ignoring means, for performing operations other than said sampling and said correlating during times at which ignoring means is ignoring samples.

4. The circuit of claim 3 wherein said means for performing includes means, responsive to said ignoring means, for assuming an idle mode for purposes of reducing circuit power consumption.

5. The circuit of claim 1 wherein said means for ignoring establishes a bit interval occurring within said observation interval between approximately 0.06 T1 and approximately 0.18 T1, wherein T1 is defined to be the time duration of the observation interval.

6. The circuit of claim 1 wherein said means for ignoring establishes a bite interval centered at approximately 0.12 T1 in the observation interval wherein T1 is defined to be the time duration of the observation interval.

7. The circuit of claim 1 wherein said ignoring means further includes weighting means, coupled to said sampling means, for weighting each of said unignored samples with a weighting factor consisting of a numeric constant and for weighting each of said ignored samples with a weighting factor of 0.0.

8. The circuit of claim 7 wherein said numerical constant is equal to 1.0.

9. The circuit of claim 1 wherein said portion of said samples includes a plurality of samples.

10. A decoder circuit for detecting the presence of a signal exhibiting a predetermined frequency comprising:

timing means for generating observation interval signals;

sampling means, responsive to said timing means, for sampling a first signal to produce samples thereof including a last sample during a substantially rectangular observation interval, said sampling means including means for ignoring a portion of said samples occurring prior to said last sample and near the end of said observation interval, and

correlation means, electrically coupled to said sampling means, for correlating said samples with a predetermined pattern to detect the presence of a signal exhibiting said predetermined frequency within said first signal.

11. The circuit of claim 10 wherein said means for ignoring further includes means for dropping a plurality of successive samples within a bite occurring in a portion of said observation interval, said bite interval having its center located between approximately 0.72 T1 and 0.98 T1, wherein T1 is defined to be the time duration of the observation interval.

12. The circuit of claim 10 including means, responsive to said ignoring means, for performing operations other than sampling and said correlating during times at which said ignoring means is ignoring samples.

13. The circuit of claim 12 wherein said means for performing includes means, responsive to said ignoring means, for assuming an idle mode for purposes of reducing circuit power consumption.

14. The circuit of claim 10 wherein said means for ignoring establishes a bite interval occurring within said observation interval between approximately 0.82 T1 and approximately 0.94 T1, wherein T1 is defined to be the time duration of the observation interval.

15. The circuit of claim 10 wherein said means for ignoring establishes a bite interval centered at approximately 0.88 T1 in the observation interval wherein T1 is defined to be the time duration.

16. The circuit of claim 10 wherein said ignoring means further includes weighting means, coupled to said sampling means, for weighting each of said unignored samples with a weighting factor consisting of a numerical constant and for weighting each of said ignored samples with a weighting factor of 0.0.

17. The circuit of claim 16 wherein said numerical constant is equal to 1.0.

18. The circuit of claim 10 wherein said portion of said samples includes a plurality of samples.

19. A decoder circuit for detecting the presence of a a predetermined frequency within a signal, comprising:

timing means for generating observation intervals;

sampling means, responsive to said timing means, for sampling a first signal to produce samples thereof including a first sample during said obseration intervals;

sample inhibiting means, coupled to said sampling means, for inhibiting said sampling means from sampling for a predetermined portion of said observation interval, said predetermined portion of said observation interval occurring after said first sample and near the beginning of said observation interval; and

correlation means, electrically coupled to said sampling means, for correlating said samples with a predetermined pattern to detect the presence of said predetermined frequency within said first signal.

20. The circuit of claim 19 wherein said sample inhibiting means further includes weighting means, coupled to said sampling means, for weighting each of said samples with a weighting factor consisting of a numerical constant.

21. The circuit of claim 20 wherein said numerical constant is equal to 1.0.

22. The circuit of claim 19 wherein said sample inhibiting means inhibits said sampling means from taking a plurality of successive samples.

23. The circuit of claim 22 wherein said plurality of successive samples are centered about a sample located between approximately 0.02 T1 and 0.28 T1, wherein T1 is defined to be the time duration of said observation window.

24. The circuit of claim 23 wherein said succesive samples are centered about approximately 0.88 T1.

25. The circuit of claim 23 wherein said successive samples are inhibited for approximately 0.12 T1.

26. The circuit of claim 19 further including means responsive to said sample inhibiting means for performing operations other than said correlating during times when said samples are inhibited by said sample inhibiting means.

27. The circuit of claim 26 wherein said means for performing includes means, responsive to said sample inhibiting means, for assuming an idle mode for purposes of reducing power consumption.

28. A decoder circuit for detecting the presence of a a predetermined frequency within a signal, comprising:

timing means for generating observation intervals;

sampling means, responsive to said timing means, for sampling a first signal to produce samples thereof including a last sample during said observation intervals;

sample inhibiting means, coupled to said sampling means, for inhibiting said sampling means from sampling for a predetermined portion of said observation interval, said predetermined portion of said observation interval occurring prior to said last sample and near the end of said observation interval; and

correlation means, electrically coupled to said sampling means, for correlating said samples with a predetermined pattern to detect the presence of said predetermined frequency within said first signal.

29. The circuit of claim 28 wherein said sample inhibiting means further includes weighting means, coupled to said sampling means, for weighting each of said samples with a weighting factor consisting of a numerical constant.

30. The circuit of claim 29 wherein said numerical constant is equal to 1.0.

31. The circuit of claim 28 wherein said sample inhibiting means inhibits said sampling means from taking a plurality of successive samples.

32. The circuit of claim 31 wherein said plurality of successive samples are centered about a sample located between approximately 0.72 T1 and 0.98 T1, wherein T1 is defined to be the time duration of said observation window.

33. The circuit of claim 32 wherein said successive samples are centered about approximately 0.12 T1.

34. The circuit of claim 32 wherein said successive samples are inhibited for approximately 0.12 T1.

35. The circuit of claim 28 further including means responsive to said sample inhibiting means for performing operations other than said correlating during times when said samples are inhibited by said sample inhibiting means.

36. The circuit of claim 35 wherein said means for performing includes means, responsive to said sample inhibiting means, for assuming an idle mode for purposes of reducing power consumption.

37. A decoder for detecting the presence of a signal exhibiting a predetermined frequency comprising:

microcomputer means for processing sampled signal information, said microcomputer including a random access memory and a read only memory for storing information therein, and including a plurality of registers for facilitating processing of such information, said microcomputer means further including

sampling means for sampling a first signal to produce samples thereof including a first sample during a substantially rectangular observation window,

ignoring means, responsive to said sampling, for ignoring a portion of said samples occuring after said first sample and near the beginning of said observation window, and

correlation means for correlating said samples with a predetermined pattern to detect the presence of said predetermined frequency within said first signal.

38. The decoder of claim 37 wherein said ignoring means further ncludes means for dropping a plurality of successive samples within a bite interval occurring in a portion of said observation window occurring between approximately 0.02 T1 and 0.28 T1, wherein T1 is defined to be the time duration of the observation interval.

39. The decoder of claim 37 including means, responsive to said ignoring means, for performing operations other than said sampling and said correlating during times at which said ignoring means is ignoring samples.

40. The decoder of claim 39 wherein said means for performing includes means, responsive to said ignoring means, for assuming an idle mode for purposes of reducing decoder power consumption.

41. The circuit of claim 37 wherein said ignoring means further includes weighting means, coupled to said sampling means, for weighting each of said unignored samples with a weighting factor consisting of a numerical constant and for weighting each of said ignored samples with a weighting factor of 0.0.

42. The circuit of claim 41 wherein said numerical constant is equal to 1.0.

43. The circuit of claim 37 wherein said portion of said samples includes a plurality of samples.

45. The decoder of claim 37 44 wherein said ignoring means further includes means for dropping a plurality of successive samples within a bite interval occurring in a portion of said observation window occurring between approximately 0.72 T1 and 0.98 T1, wherein T1 is defined to be the time duration of the observation interval.

44. A decoder for detecting the presence of a signal exhibting a predetermined frequency comprising:

microcomputer means for processing digital signal information including a random access memory and a read only memory for storing information therein, and including a plurality of registers for facilitating processing of such information, said microcomputer means further including

sampling means for sampling a first signal to produce samples thereof including a last sample during a substantially rectangular observation window,

ignoring means, responsive to said sampling means, for ignoring a portion of said samples occurring prior to said last sample and near the end of said observation window, and

correlating means for correlating said samples with a predetermined pattern to detect the presence of a signal exhibiting said predetermined frequency within said first signal.

46. The decoder of claim 44 including means, responsive to said ignoring means, for performing operations other than said sampling and said correlating during times at which said ignoring means is ignoring samples.

47. The decoder of claim 46 wherein said means for performing includes means, responsive to said ignoring means, for assuming an idle mode for purposes of reducing decoder power consumption.

48. The circuit of claim 44 wherein said ignoring menas further includes weighting means, coupled to said sampling means, for weighting each of said unignored samples with a weighting factor consisting of a numerical constant and for weighting each of said ignored samples with a weighting factor of 0.0.

49. The circuit of claim 48 wherein said numerical constant is equal to 1.0.

50. The circuit of claim 44 wherein said portion of said samples includes a plurality of samples.

51. A method of processing a particular signal to determine if said particular signal exhibits a predetermined frequency comprising the steps of:

generating an observation interval signal;

sampling said particular signal during the observation window established by said observation interval signal, to produce samples of said particular signal including a first sample;

ignoring a portion of the samples of said particular signal occurring in time after said first sample and near the beginning of said observation window, and

correlating the samples of said particular signal which are not ignored with a predetermined pattern to detect the presence of said predetermined frequency.

52. The method of claim 51 wherein said observation window exhibits a time duration of T1 units of time and said bite interval exhibits a bite position within the range of approximately 0.06 T1 and approximately 0.18 T1.

53. A method of processing a particular signal to determine if said particular signal exhibits a predetermined frequency comprising the steps of:

generating an observation interval signal;

sampling said particular signal during the obsevation window established by said observation interval signal, to produce samples of said particular signal including a last sample;

ignoring a plurality of the samples of said particular signal occurring in time prior to said last sample and near the end of said observation window, and,

correlating the samples of said particular signal which are not ignored with a predetermilned pattern to detect the presence of a signal exhibiting said predetermined frequency.

54. The method of claim 53 wherein said observation window exhibits a time duration of T1 units of time and said bite interval exhibits a bite position within the range of approximately 0.82 T1 and approximately 0.94 T1.

55. A method of providing a computer with processing time for performing other tasks when said computer is functioning as a correlator for correlating a sampled signal with a predetermined pattern to determine the presence of a predetermined frequency, said method comprising the steps of:

sampling a first signal to produce samples thereof including a first sample during a first time segment of a predetermined observation window;

interrupting said sampling for a second time segment of said predetermined observation window to enable said computer to perform said other task thereby effectively ignoring said first signal during said second time segment;

sampling said first signal for the remainder of said predetermined observation window to produce samples thereof including a last sample; and

correlating said samples with said predetermined pattern to determine the presence of said predetermined frequency for a first time segment of said observation window.

56. The method of claim 55 wherein said second time segment occurs after said first sample and near the beginning of said observation window.

57. The method of claim 55 wherein said second time segment occurs prior to said last sample and near the end of said observation window.

58. The method of claim 56 wherein said second time segment is centered between approximately 0.02 T1 and 0.28 T1, wherein T1 is defined to be the duration of said observation window.

59. The method of claim 57 wherein said second time segment is centered between approximately 0.72 T1 and 0.98 T1, wherein T1 is defined to be the duration of said observation window.