Simultaneous self-testing system

• US 4,513,418 A
• Filed: 11/08/1982
• Issued: 04/23/1985
• Est. Priority Date: 11/08/1982
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McAnney, William H., Bardell, Paul H. Jr.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/440,070
• Time in Patent Office: 897 Days
• Field of Search: 371/25, 371/15, 324/73 R, 324/73 AT
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

The LSSD scan paths on a number of logic circuit chips are modified and connected together in series to simultaneously serve as a random signal generator and data compression circuit to perform random stimuli signature generation.

Claims

1. In a combinational and sequential logic circuit with memory circuits on individual logic units coupled together to form a shift register scan path for testing logic circuits and uncoupled to disable the scan path while the logic circuit is performing its designed logic function, a method for performing self-testing using a multistage generator means to generate testing sequences for the self-testing and multistage data compression means to compress the responses of the logic circuits comprising:

(a) forming the shift register scan path on the logic unit into a single linear feedback shift register means capable of forming multistage random signal generator means for a multistage data compression means,

(b) shifting data through said linear feedback shift register means to transmit the data as a test input from memory circuits of said linear feedback shift register means and simultaneously capture the response to the shifted data in the same memory circuits of said linear feedback shift register means;

(c) using the captured response to the shifted data as a further test input transmitted from said memory circuits of said linear feedback shift register means and capturing the response to said further test input in the same memory circuits;

(d) repeat step (c) n times;

(e) reading the contents of said linear feedback means out of said scan path after step (d) as the test result.

2. In a combinational and sequential logic circuit with memory circuits on individual logic units coupled together to form a shift register scan path for testing logic circuits and uncoupled to disable the scan path while the logic circuit is performing its designed logic function, a method for performing self-testing using a multistage generator means to generate testing sequences for the self-testing and a multistage data compression means to compress the responses of the logic circuits the improvement comprising:

(a) first using the scan path to introduce a preset data pattern into the memory circuits of the scan path;

(b) changing the stages of the shift register scan path into a linear feedback shift register means capable of function as a multistage random signal generator means and a multistage data compression means, after the preset data pattern has been introduced into the memory circuits;

(c) shifting data through said linear feedback shift register means so that it simultaneously supplies a test output and captures response of the logic circuit to the test input;

(d) using the captured response to the shifted data as a further test input transmitted from said memory circuits of said linear feedback shift register means and capturing the response to said further test input in the same memory circuits;

(e) repeat step d n times;

(f) reading the contents of said linear feedback shift register means as the test result after a plurality of shifting cycles as recited in step (d) have been performed by the linear feedback shift register means.