Hall effect device test circuit

• US 4,514,687 A
• Filed: 07/07/1982
• Issued: 04/30/1985
• Est. Priority Date: 07/07/1982
• Status: Expired due to Fees

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: GTE Automatic Electric Incorporated (Verizon Communications Inc.)
• Inventors: Van Husen, Hendrik W.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US06/396,177
• Time in Patent Office: 1,028 Days
• Field of Search: 324/158 R, 324/158 D, 324/202, 324/228, 324/74, 307/309
• US Class Current: 324/537
• CPC Class Codes: G01R 33/07 Hall effect devices
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A test circuit which detects Hall effect device operate and release time failures. This circuit includes a magnetic field circuit, a comparison circuit, a storage circuit and a visual indication circuit. The magnetic field circuit causes a Hall effect device under test to periodically switch states. The operate and release times of such switching is compared to predetermined thresholds by the comparison circuit. Switching times within the allowable thresholds cause the storage circuit to operate the visual indication circuit.

Claims

1. A Hall effect device test circuit for use in a test system including a power signal source, said test circuit comprising:

magnetic field means connected to said power signal source, operated in response to said power signal to periodically provide a magnetic field of varying intensity;

voltage reference means connected to said power source, operated in response to said power signal to periodically provide a sample voltage of varying magnitude and proportional to the intensity of said magnetic field;

a Hall effect device connected in magnetic field proximity to said magnetic field means, operated in response to each magnetic field of a first predetermined intensity to provide an operate signal, and operated in response to each magnetic field of a second predetermined intensity to provide a release signal;

comparison means connected to said voltage reference means operated in response to said sample voltage having a magnitude less than a first predetermined threshold to provide a first comparison signal and further operated in response to said sample voltage having a magnitude greater than a second predetermined threshold to provide a second comparison signal;

storage means connected to said comparison means and said Hall effect device, operated in response to each operate signal and said first comparison signal to provide a first storage signal and further operated in response to each release signal and said second comparison signal to provide a second storage signal; and

signaling means connected to said storage means, operated in response to said first storage signal to provide a first status signal and further operated in response to said second storage signal to provide a second status signal.

2. A Hall effect device test circuit as claimed in claim 1, wherein:

said signaling means is further operated in response to said first and second storage signals to provide a third status signal.

3. A Hall effect device test circuit as claimed in claim 1, wherein:

said storage means is further operated in response to each operate signal and an absence of said first comparison signal to inhibit said first storage signal and further operated in response to each release signal and an absence of said second comparison signal to inhibit said second storage signal.

4. A Hall effect device test circuit as claimed in claim 1, wherein said magnetic field means comprises:

an electromagnet connected to a diode, whereby said magnetic field is unidirectional.

5. A Hall effect device test circuit as claimed in claim 1, wherein said voltage reference means comprises:

a resistor.

6. A Hall effect device test circuit as claimed in claim 1, wherein there is further included first and second threshold determining means, said comparison means comprising:

a first comparator including a first input connected to said first threshold determining means and a second input connected to said voltage reference means; and

a second comparator including a first input connected to said voltage reference means and a second input connected to said second threshold determining means, whereby said first comparator provides said first comparison signal and said second comparator provides said second comparison signal.

7. A Hall effect device test circuit as claimed in claim 1, wherein said storage means comprises:

a first D-type flip-flop having a data input connected to said comparison means and a clock input connected to said Hall effect device;

an inverter connected to said Hall effect device; and

a second D-type flip-flop having a data input connected to said comparison means and a clock input connected to said inverter.

8. A Hall effect device test circuit as claimed in claim 1, wherein said signaling means comprises:

a first visual indicator operated to provide said first status signal.

9. A Hall effect device test circuit as claimed in claim 1, wherein said signaling means further comprises:

a second visual indicator operated to provide said second status signal.

10. A Hall effect device test circuit as claimed in claim 2, wherein said signaling means further comprises:

a third visual indicator operated to provide said third status signal.

11. A Hall effect device test circuit as claimed in claim 8, wherein said first visual signaling means comprises:

a light emitting diode.

12. A Hall effect device test circuit as claimed in claim 9, wherein said second visual signaling means comprises:

a light emitting diode.

13. A Hall effect device test circuit as claimed in claim 10, wherein said third visual signaling means comprises:

a light emitting diode.

14. A Hall effect device test circuit as claimed in claim 6, wherein:

said first and second threshold determining means each comprise a potentiometer.

15. A Hall effect device test circuit as claimed in claim 7, wherein:

said data input of said first D-type flip-flop is connected to said first comparator and said data input of said second D-type flip-flop is connected to said second comparator.