Data transfer system for a data processing system provided with direct memory access units

• US 4,514,808 A
• Filed: 05/11/1982
• Issued: 04/30/1985
• Est. Priority Date: 04/28/1978
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Murayama, Masaki, Iida, Manjiro
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/377,044
• Time in Patent Office: 1,085 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/307
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

A data transfer system is disclosed which includes a main memory, a memory control unit for controlling the operation of the main memory, a central processing unit, a plurality of direct memory access units each provided with at least two data transfer bus widths, a common data bus line, and a common memory address/control line. A control line is provided for distinguishing between the at least two data transfer bus widths and is only connected between a direct memory access unit provided with the memory control unit, the central processing unit and one of the at least two data transfer bus widths. When data is transferred, using one of the data transfer bus widths, the control line is energized with a control signal which is delivered to the memory control unit. On the other hand, the direct memory access unit which has the other data transfer bus width is not connected to the control line thereby preventing it from becoming energized.

The memory control unit controls the operation of a gate circuit between the memory data line which is connected between the main memory and the data bus line and the read data line and generates a write enable signal for effecting a writing of data in byte units in either an even number address or an odd number address thereof.

Claims

1. In a data processing system which includes a central processing unit with an n-bit word length, where n is a positive integer having a value greater than 7, a main memory, a plurality of direct memory access units and an n-bit data bus coupling the central processing unit, the main memory and the direct memory access units for transfer of data between the direct memory access units and the main memory, the improvement comprising a data transfer system for accessing the main memory, the data transfer system comprising:

(a) said main memory being capable of storing n-bit full-words in byte units, each full-word made up of m bytes where n/m is the number of bits in one byte and said memory having a separate transfer enable input for each of said m bytes;

(b) said direct memory access units comprising at least one first direct memory access unit which can receive and deliver n-bit full-words, and at least one second direct memory access unit which can receive and deliver n/2 bit half-words, since n/2 is an integer;

(c) a plurality of gate circuits coupling the main memory and the data bus line;

(d) first data transfer control means for controlling the gate circuits so that data transfer is achieved between the main memory and the first direct memory access unit, using n bits of the data bus line and an n-bit memory location when the first direct memory access unit has access to the main memory;

(e) zone specifying means having m zone selection inputs from the Central Processing unit, one corresponding to each of said m bytes in said main memory and responsive to said zone selection inputs and a control output from said first data transfer control means indicative of data transfer between the main memory and the first direct memory access unit, for selectively providing at least one signal to said separate transfer enable inputs to enable, transfer of at least one byte of data between an n-bit memory location and said first direct memory access unit using a corresponding part of the n-bit data bus line and the first direct memory access unit whereby through use of said zone specifying means appropriate zones within an n-bit full-word or a half-word may be specified; and

(f) second data transfer control means for controlling the gate circuits so that data transfer is achieved between the main memory and the second direct memory access unit, using n/2 bits of the data bus line and n/2 bits from an n bit memory location when the second direct memory access unit has access to the main memory.

2. The data transfer system according to claim 1, further comprising a memory control unit including said first and second data transfer control means and said zone specifying means, a common address/control line for transferring an address and a command from said first and second direct memory access units to said memory control unit, a mode control line for transferring a mode control signal from said first direct memory access unit to said memory control unit, and a zone designation line for transferring a zone specifying signal from said first direct memory access unit to the memory control unit, said zone specifying signal designating for transfer at least one byte from an n-bit memory location using a corresponding part of the n-bit data bus line wherein the memory control unit actuates the first data transfer control means and the zone specifying means in response to the mode control signal and the zone specifying signal transferred to the memory control unit from the first direct memory access unit on the mode control line and the zone designation line, respectively, and controls data writing in the main memory in accordance with the address and command transferred to the memory control unit from the first direct memory access unit on the common address/control line.

3. The data transfer system according to claim 1, further comprising a memory control unit including said first and second data transfer control means and said zone specifying means, a common address/control line for transferring an address and a command from the first and second direct memory access units to the memory control unit, and a zone designation line for transferring a zone specifying signal from said first direct memory access unit to the memory control unit, said zone specifying signal designating for transfer at least one byte within an n-bit memory location using a corresponding part of the n-bit bus line and selection of said first data transfer control means, wherein the memory control unit actuates said first data transfer control means and said zone specifying means in response to the zone specifying signal transferred from the first direct memory access unit on the zone designation line and controls data writing in the main memory in accordance with the address and command transferred to the memory control unit from the first direct memory access unit on the common address/control line.

4. The data transfer system according to claim 3, wherein said memory control unit actuates said second direct memory access unit and controls data reading and data writing from and to respectively, the main memory in accordance with the address and command transferred to said memory control unit from said second direct memory access unit on said common address/control line in the absence of a signal on said zone designation line from said first direct memory access unit.

5. The data transfer system according to claim 1 wherein said the system is adaptable to both an n equal to thirty-two and an n equal to sixteen and to both an m equal to four and an m equal to two.

6. The data transfer system according to claim 1 wherein n is thirty-two and m is four.